AMBA interface circuit

Abstract

The invention relates to an AMBA interface circuit which is characterized in that 3 FIFOs are arranged in a Master interface circuit, wherein the Writer Data FIFO and the Writer Address FIFO are used for receiving the data and the address from the transmission of master equipment; if the master equipment does not obtain the right to use the bus temporarily, the data or the address can be first written into the Writer Data FIFO or the Writer Address FIFO, and the data or the address can be transmitted after the master equipment obtains the right to use the bus; the Read Data FIFO is used for sending data to the master equipment; when the master equipment is busy, the data from the transmission of a Slave equipment can be stored temporarily in the Read Data FIFO, then the bus can be release, and the data can be transmitted when the master equipment can receive the data. Compared with the prior art, the invention has the advantages that firstly, because the FIFOs are arranged in the Master interface circuit, the running of the master equipment and the slave equipment and the transmission of the data or the address can be made concurrent, and the bus waiting time and the access-memory delay can be can be shortened, secondly, because the FIFOs are arranged in the Master interface circuit, the resource can be saved in the process of the transmitting the data or the address by the master equipment and the slave equipment, and thirdly, the loss of the data can be avoided when the Master interface circuit is used for transmitting the network on the chip.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits and relates to an AMBA bus interface circuit. Background technique [0002] Microprocessor core or DSP core, memory, system bus and peripherals have been integrated on one chip. With the development of SoC technology, high-speed data transmission is required to reduce bus access delay and memory access delay. It is necessary to design a bus interface module that can meet high-speed data transmission, so that the operation of the processor core and the data transmission of the peripherals have parallelism, and improve the overall performance of the system. [0003] At present, such as the integrated circuit with the patent No. 02130330.4 and the method of data conversion between the AHB interface of AMBA and the parallel processor in the RISC system of 20071004557.7, most of the interface circuits based on the AMBA bus use registers to transmit data, and it is difficult to...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is exactly in order to overcome the bus access delay that exists in the interface circuit of existing AMBA bus, the defective that wastes resources easily, a kind of AMBA interface circuit that adopts FIFO to store and read and write is provided

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