Method for obtaining circuit performance after considering related stress of layout

Abstract

The invention relates to a method for obtaining the circuit performance after considering the related stress of a layout, belonging to the technical field of integrated circuit designs. The method comprises the following steps: extracting all transistor areas of the layout; marking out the effective area for each transistor in the layout, and dividing a large-scale circuit into small units; setting an initial condition and a boundary condition according to the three dimensional structure of the effective area of each transistor in the layout structure, adopting a general finite element method to solve to obtain three-dimensional stress distribution of the effective area of each transistor; calculating the mobility rate of each transistor after considering the influence of the related stress of the layout, using the mobility rate to update an original transistor model, using a new transistor model to calculate to obtain the circuit performance after considering the influence of the related stress of the layout. The invention has the advantages that the grid updating process is simplified, the simulation speed and the simulation scale are improved, the calculating result is accurate, and complex layout structures can be processed, and the like.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, relates to an integrated circuit design considering the influence of layout-related stress on circuit characteristics, and in particular relates to a method for obtaining the influence of stress introduced by an STI process on circuit characteristics. Background technique [0002] With the development of integrated circuit technology, stress has been widely studied as a factor affecting the performance of transistor devices. A variety of different processes are employed to artificially introduce additional stress to achieve the desired change in device performance. A typical strained channel technology is used to epitaxially grow a Si layer for making devices on a SiGe substrate. Since the lattice constants of Si and SiGe layers are different, biaxial tensile stress in the channel plane will be introduced into the Si layer. The introduction of this stress affects the valence b...

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Problems solved by technology

[0007] The purpose of the present invention is to solve the problem that it is difficult to solve the influence of layout-related stress on circuit characteristics of large-scale circuits in the prior art, and propose a method for obtaining the influence of layout-related stress on circuit characteristics in integrated circuits. The present invention adopts piezoresistive migration The rate model calculates the change of carrier mobility caused by the layout-related stress, and applies it to the transistor model, and finally obtains the circuit characteristics after considering the layout-related stress

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