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Method for mapping task of network on two-dimensional grid chip

A two-dimensional grid and network-on-chip technology, which is applied to instruments, multi-channel program devices, and electrical digital data processing, can solve problems such as long execution time and unguaranteed degree of optimization

Active Publication Date: 2010-01-13
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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Problems solved by technology

[0004] The purpose of the present invention is to overcome the problem that the mapping method in the prior art takes a long time to execute and the degree of optimization of the final solution cannot be guaranteed, thereby providing a task mapping method for a two-dimensional grid on-chip network

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  • Method for mapping task of network on two-dimensional grid chip
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  • Method for mapping task of network on two-dimensional grid chip

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specific Embodiment approach

[0058] Based on the above theoretical calculation, the specific implementation of the present invention is as follows:

[0059] Suppose that in a certain task, the number of special threads is S, and the number of ordinary threads is T-S. All special threads are listed in a sorted queue, and all ordinary threads are also added to the queue. Preferably, ordinary threads can be added to the queue in order according to the size of the communication volume between the thread and other threads in the queue. Take a pair of threads with the largest amount of communication, including at least one ordinary thread that has not yet joined the queue. If two threads are not in the queue, both threads are attached to the end of the queue. Their order depends on the maximum communication volume between these two threads and other threads in the queue, with the larger value first; If one is already in the queue, another thread is added to the end of the sorting queue. Then take the next pair o...

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Abstract

The invention discloses a method for mapping a task of a network on a two-dimensional grid chip. The method comprises the following steps: 1) pre-distributing expected positions of all threads on a two-dimensional grid, wherein the threads comprise common threads which can be mapped to any position; 2) calculating variation Com_diff of a general communication power consumption factor after each common thread is exchanged with a close-by common thread on the expected position of the common thread or an idle position, wherein the common thread executes exchange with the common thread or the idle position which minimizes the Com_diff, until exchanges of all the common threads and the close-by threads on the expected positions of the common threads or the idle positions lead the Com_diff to be more than or equal to zero; and 3) outputting a mapping file according to the positions of all the threads. The method has high optimization degree, and solves part of the mapping problem because users can regulate parameters by oneself to control time complexity.

Description

Technical field [0001] The invention relates to a method for using a multi-core processor, which is a task mapping method of a network-on-chip (NoC) with a two-dimensional mesh (2-D Mesh) structure. Background technique [0002] With the development of semiconductor and integrated circuit technology, the integration of System-on-Chip (SoC) is getting higher and higher. A single chip can integrate hundreds of IPs such as microprocessors, memories, and I / O interfaces. nuclear. On the other hand, the functions of embedded electronic products are becoming more and more complex, and single-processor system-on-chips can no longer meet the increasing functional and performance requirements of embedded systems. The emergence of multi-core system-on-chips (Multi-Processor SoC, MPSoC) has become inevitable. The multi-core system on chip puts forward higher requirements for on-chip communication, and the network on chip is proposed to solve the global communication of the multi-core system...

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Application Information

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IPC IPC(8): G06F15/177G06F9/46
Inventor 刘祥陈曦黄毅张金龙任菲
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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