Method for optimizing on-chip network structure by adding bypass in processor

An on-chip network and processor technology, applied in data exchange networks, machine execution devices, digital transmission systems, etc., can solve problems such as network inoperability, delay, deadlock, etc., and achieve function expansion, high efficiency, and reduced energy consumption Effect

Inactive Publication Date: 2009-09-16
ZHEJIANG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Deadlock often occurs in the transmission of the network on chip, which will cause a large amount of delay, and even affect the failure of the entire network on chip

Method used

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  • Method for optimizing on-chip network structure by adding bypass in processor
  • Method for optimizing on-chip network structure by adding bypass in processor

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Embodiment Construction

[0022] The present invention will be further described below in conjunction with drawings and embodiments.

[0023] Processor core improvement and system-on-chip integration architecture can be divided into three modules: the improved processor module, the router module of the network on chip, and other modules of the network on chip. Since this method is optimized from the perspective of the processor and has no connection with other modules of the network on chip, only the first two modules are discussed below.

[0024] The improved processor module divides the processor into two parts: the processor part and the added module part. The processor module is in figure 1 Including IF (instruction fetching module), ID (instruction analysis / read register cycle), EXE (execution cycle), MEM (write back memory), WB (write back cycle), L1Cache module. The added modules mainly include Forecaster (prediction module), Register (latch module), including bypass and connected wires.

[0...

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Abstract

The invention discloses a method for optimizing the on-chip network structure by adding a bypass in a processor. In the invention, the bypass is added in the processor and the auxiliary module is added to support the lower delayed on-chip network structure. In the invention, the processor can be used for not only transmitting the treated result, but also transmitting the intermediate result temporarily stored in the treatment process, for the other node processor, the more data can be obtained, the treating function of the network on the whole chip can be extended. For the thread with the higher data dependence, a large number of data treatment and transmission can be performed between the threads, the execution efficiency is higher. The invention can improve the processor to better support the on-chip network structure and performing the on-chip network advantages.

Description

technical field [0001] The invention relates to the internal structure of a processor core and an on-chip network architecture, in particular to a method for adding a bypass in a processor to optimize the on-chip network architecture. Background technique [0002] There are four completely independent aspects of the on-chip design: Compute, Storage, Communication, I / O. With the increasing processing power of processors and the continuous emergence of data-intensive applications, the system on chip (SOC-SystemOn Chip) is facing challenges in communication. This challenge has attracted more and more attention and led to the concept of Network On Chip (NOC-Network On Chip). Network-on-chip is not a new option for on-chip communication, it is a concept that provides a unified solution for on-chip communication. The network on chip is a bit like a macro network, which can be effectively expanded with the increase of nodes, where the nodes include data processing parts, such as ...

Claims

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Application Information

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IPC IPC(8): H04L12/56G06F9/38H04L12/701
Inventor 陈天洲缪良华汪达舟王超陈剑
Owner ZHEJIANG UNIV
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