Chemical mechanical grinding method and wafer cleaning method
A technology of chemical machinery and grinding method, which is applied in the direction of chemical instruments and methods, cleaning methods and utensils, cleaning methods using liquids, etc. It can solve the problem of easily remaining abrasive particles on the wafer, reduce the number of particle defects, and improve the repair quality Effect
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no. 1 example
[0066] This example introduces a new method of planarizing a metal layer by using a chemical mechanical polishing process. The metal layer can be metal copper or metal tungsten or the like.
[0067] Image 6 It is a flowchart of the chemical mechanical polishing method in the first embodiment of the present invention, Figure 7 to Figure 11 In order to illustrate the device cross-sectional view of the first embodiment of the present invention, below in conjunction with Figure 6 to Figure 11 The first embodiment of the present invention will be described in detail.
[0068] Step 601: Place the wafer to be polished in chemical mechanical polishing equipment, and the dielectric layer, the through-hole opening in the dielectric layer, and the through-hole opening and on the dielectric layer have been formed on the wafer metal layer.
[0069] Figure 7 It is a schematic cross-sectional view of the device before the chemical mechanical polishing method is used to planarize the...
no. 2 example
[0102] The present invention also correspondingly provides a wafer cleaning method after grinding. Figure 12 It is the flowchart of the wafer cleaning method in the second embodiment of the present invention, below in conjunction with Figure 12 The second embodiment of the present invention will be described in detail.
[0103] The wafer cleaning method in the present embodiment comprises steps:
[0104] Step 1201: Provide a ground wafer, and the wafer has a dielectric layer, a via opening located in the dielectric layer, and a metal structure located in the via opening, and the metal structure is higher than the medium layer.
[0105] The ground wafer provided in this embodiment is as Figure 9 As shown, the substrate 701 may be a substrate on which metal oxide semiconductor transistors have been formed, or may be a substrate on which an underlying metal wiring structure has been formed. The dielectric layer 702 formed on the substrate 701 may be a silicon oxide layer f...
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