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Parameter computation method of RFCMOS model with expandability

A parameter calculation and model technology, applied in the direction of calculation, electrical digital data processing, special data processing applications, etc., can solve problems such as poor scalability, and achieve the effects of improving model accuracy, achieving scalability, and reducing design costs.

Active Publication Date: 2009-06-17
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0006] Due to the particularity of RFCMOS layout design, figure 1 Most of the RFCMOS models shown are limited to simulating RFCMOS devices of a certain size or a small range of sizes, and the scalability is poor

Method used

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  • Parameter computation method of RFCMOS model with expandability
  • Parameter computation method of RFCMOS model with expandability
  • Parameter computation method of RFCMOS model with expandability

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Embodiment Construction

[0015] In RFCMOS circuit design, in order to reduce the impact of gate parasitic resistance and various parasitic PN junctions on the high frequency performance of RFCMOS devices, RFCMOS devices generally adopt a multi-gate parallel layout structure (Multi-finger structure). see figure 2 RFCMOS devices with a parallel gate count of 2 are shown and image 3 The schematic diagram of an RFCMOS device with four parallel gates is shown, and its layout parameters include transistor channel length L, transistor channel width W, and the number nf of transistor parallel gates.

[0016] exist figure 1 In the RFCMOS model shown, the source resistor R S and drain resistance R D It can be comprehensively reflected by the parameter Rdsw of the BSIM3v3 model. The parameter Rdsw represents the source-drain parasitic resistance per unit width (Parasitic resistance per unit width), so the source resistance R S and drain resistance R D It does not need to be calculated separately, and can ...

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Abstract

The invention discloses a parameter calculation method for RFCMOS models of expansibility. The model adds a sub circuit based on the MOS field transistor of BSIM3V3 model, wherein the sub circuit comprises a parasitic resistance of grid electrode, a parasitic resistance of source electrode, a parasitic resistance of drain electrode and a substrate network. The substrate network comprises a parasitic diode between the source electrode and the substrate, a parasitic diode between the drain electrode and the substrate, a coupling resistance between the source electrode and the substrate, a coupling resistance between the drain electrode and the substrate, and a coupling resistance of the substrate. The parasitic resistance of the grid electrode and the components forming the substrate network are calculated from variable parameters which at least comprise one of transistor channel length, channel width and the number of parallel grid electrodes. The parameter calculation method improves model precision, effectively realizes model expansibility and effectively reduces the design cost of radio frequency circuits.

Description

technical field [0001] The present invention relates to an RFCMOS (Radio Frequency CMOS) model. Background technique [0002] With the continuous development of CMOS technology, deep submicron CMOS devices have the characteristics of high-frequency signal transmission and low noise, so they are more and more used in radio frequency (RF) circuit design and widely used in the field of wireless communication. [0003] In RFCMOS circuit design, only by establishing an accurate RFCMOS model can the performance of RFCMOS devices be accurately simulated during circuit simulation, thereby saving the RFCMOS circuit design cycle. The RFCMOS model requires more emphasis on describing high-frequency performance such as nonlinearity, high-frequency noise, and non-quasi-static effects of RFCMOS devices on the basis of including all low-frequency characteristics. [0004] So far, there is no standard RFCMOS model in the industry, and RFCMOS devices are usually simulated by adding branch c...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 武洁李平梁
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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