Planar MOSFET integrated with schottky diode and its layout method

Abstract

A planar MOSFET integrated with Schottky diodes manufactured without additional masks and layout method. A semiconductor power device supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

Description

technical field [0001] The present invention relates to a semiconductor power device, in particular to an improved and novel manufacturing process and device structure for integrating a silicon carbide mixed Schottky tube onto a planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor). No additional masks are required to improve high frequency power conversion, H-bridge and synchronous rectification applications. Improved body diode recovery results in lower losses and lower voltage oscillations in the power circuit without compromising the layout of the integrated MOSFET Schottky device. Background technique [0002] In order to reduce power loss in semiconductor power devices while increasing their switching speed, further reductions in on-resistance and gate capacitance are desired. Integrals in which Schottky diodes are disposed over semiconductor power devices such as Metal Oxide Silicon Field Effect Transistors (MOSFETs) have been used. In addition to the de...

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Problems solved by technology

However, the high barrier height metal required to achieve a suitably low leakage current in the off state has the disadvantage of meeting the Schottky ohmic contact and the source-body ohmic contact at the same time. Depositing high barrier height metals and lower barrier height metals incurs higher cost

[0006] In addition, in Figure 1A , Figure 1B and figure 2 The device structure shown in is still subject to the Figure 1C and Figure 1D The bottom corner of the P+ pocket region shown in is easily limited by the breakdown characteristics. The breakdown is easy to occur at the bottom corner of the body-type doped (P+ pocket) region because of the vicinity of the bottom corner of the P+ pocket region. Due to the small radius of curvature of the PN junction

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