Method for forming stress layer of complementary metal oxide semiconductor device

Abstract

The invention discloses a formation method of a stress layer of a CMOS device, which comprises the following steps; a tensile stress layer is formed on the surfaces of an NMOS transistor and a PMOS transistor; a positive photoresist is coated on the surface of the tensile stress layer; the positive photoresist is patterned by utilizing a mask blank so as to form a photoresist mask pattern exposing on the tensile stress layer on the surface of the PMOS transistor; the tensile stress layer on the surface of the PMOS transistor is etched and the photoresist mask pattern is removed; a compressive stress layer is sedimentated on the tensile stress layer and the surface of the PMOS transistor; a negative photoresist is coated on the surface of the compressive stress layer; the negative photoresist is patterned by utilizing the mask blank so as to form a photoresist mask pattern exposing on the compressive stress layer on the surface of the NMOS transistor; the compressive stress layer on the surface of the NMOS transistor is etched and the photoresist mask pattern is removed. The formation method of the invention can form the photoresist mask patterns of the tensile stress layer and the compressive stress layer just by using the same mask blank, thus not only reducing the manufacturing cost but also promoting the precision of connection of the tensile stress layer with the compressive stress layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a stress layer of a complementary metal oxide semiconductor device (CMOS). Background technique [0002] In semiconductor manufacturing technology, it is known that the formation of a stress layer on a doped region can generate mechanical stress on the underlying layer or substrate containing doped impurities, through which the speed of the associated semiconductor device can be increased. Such stress can increase the mobility of dopant impurities. The increased mobility of dopants or charge carriers enables semiconductor devices to operate at higher speeds. In the past ten years, the operation speed, performance, circuit element density and cost of each functional element of integrated circuits have been continuously improved by reducing the size of metal oxide semiconductor field effect transistors (MOSFETs). The reduction method mainl...

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Problems solved by technology

When the stress layer 18 is deposited, the stress layer covers the previously formed stress layer 16, so after removing the photoresist pattern 50', it is easy to have a raised phenomenon at the junction of the stress layer 156 and 18

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