Structure for testing integrality of grid medium layer, forming method and test method thereof

Abstract

A forming method of a grid dielectric layer integrality test structure includes: forming an insulated groove in a semiconductor substrate as active region insulation; sequentially forming a dielectric layer, a multi-crystal silicon layer and an electrode layer on the semiconductor substrate; etching the dielectric layer, the multi-crystal silicon layer and the electrode layer to sequentially form a grid dielectric layer, a grid multi-crystal silicon layer and a grid electrode layer. Accordingly, the invention provides a test structure and a test method for grid dielectric layer integrality. The grid dielectric layer integrality test structure is formed by two layers of mask board and has analogous electricity test result to an existing grid dielectric layer integrality test structure formed by employing four layers of mask board, synchronously electricity test result repeatability of the grid dielectric layer integrality test structure of present invention is good, thereby saving technique cost, shortening technique circulation period and reducing technique risk.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a test structure for the integrity of a gate dielectric layer, a forming method and a test method thereof. Background technique [0002] Since the gate dielectric layer plays an important role in the integrated circuit (IC), the control of the gate dielectric layer integrity (GOI) is very important in the IC manufacturing industry. There are many reports on how to prepare the gate dielectric layer in current patents. For example, the Chinese patent applications with application number 200510129150 and application number 200510081046 provide the process of how to prepare the gate dielectric layer, but do not disclose how to test the integrity of the gate dielectric layer. . The integrity of the gate dielectric layer includes indicators such as the insulation of the gate dielectric layer and the crystal quality of the gate dielectric layer. In the prior art, because the pr...

AI Technical Summary

Problems solved by technology

The cycle period for preparing the test structure for the integrity of the above-mentioned gate dielectric layer is relatively long, generally taking more than two weeks. Due to the long cycle time, the corresponding risk increases. For example, when the gate dielectric layer is found to be defective, there are already defects on the process line. Many wafers form the gate dielectric layer, and these products will be affected accordingly

At the same time, since the test structure for the integrity of the gate dielectric layer needs to go through many processes such as growth, photolithography, and etching, the process cost is increased.

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