FIFO memory implementing method and apparatus

Abstract

The invention provides a first in first out memory device, which comprises a memory, a write address controller and a read address controller, the memory is connected to the read address controller and the write address controller respectively, the memory device also includes a comparator and a subtracter, wherein the comparator is connected to the write address controller and the read address controller respectively and to the memory through the substracter; the memory is a memory having at least two ports; the substracter is used for subtracting zero from a pointer difference value of the memory to get a used depth; and the comparator is used for comparing the read point and the write pointer of the memory to get a pointer difference value, and compares the used depth with the memory depth and a predefined full value to get full, to fill and predefined full state signals for feed-backing to the write address controller, besides, the comparator is used for comparing the used depth with zero to get empty and to empty state signals for feed-backing to the read address controller. The invention also provides a realizing method of the device, such that the FIFO control of data cache becomes better and more convenient.

Description

technical field [0001] The invention relates to the field of data communication, in particular to a method and device for implementing a data transmission first-in-first-out memory of an integrated circuit. Background technique [0002] The data buffer unit is an indispensable hardware unit when realizing the communication system. In FPGA (Field Programmable Gate Array, Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit), major manufacturers have developed their own FIFO (First In First Out) units for users to use. Including synchronous FIFO and asynchronous FIFO modules. In order to ensure that the data is written or read correctly without overflow or read empty state, it must be ensured that the FIFO cannot be written when it is full; and that it cannot be read when it is empty. Therefore, the difficulty of FIFO design lies in how to judge the empty / full state of FIFO. [0003] The interface structure of the traditional FIFO unit is as foll...

AI Technical Summary

Problems solved by technology

[0011] In this traditional FIFO interface structure, there is one biggest defect: the control signal is too simple

However, in some data transmission situations, for example, when data needs to be written or read in blocks, it is not enough for FIFO to provide only the above-mentioned signals. Users may need to know the remaining data space of this FIFO, or try to specify a The predetermined value of the full signal or empty signal, when transmitting block data or group data, it is hoped to judge the empty and full state of the FIFO in advance

To sum up, due to the defects in the controllable functions of the FIFO unit, the user's operation is limited

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