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Method for etching inclined shoulder type side wall in large scale integrated circuit logic device

A technology of large-scale integrated circuits and logic devices, which is applied in the manufacturing of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the problems of polysilicon gate pitch size PMD deposition voids and other problems, achieve good in-plane uniformity, and reduce leakage loss. , the effect of reducing the loss

Active Publication Date: 2008-06-18
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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AI Technical Summary

Problems solved by technology

[0007] The technical problem to be solved in the present invention is to provide a method for etching the sloping shoulder type sidewall of a VLSI logic device, which solves the problem that the follow-up PMD deposition produces voids due to the continuous reduction of the pitch size of the polysilicon gate, Improve device reliability

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  • Method for etching inclined shoulder type side wall in large scale integrated circuit logic device
  • Method for etching inclined shoulder type side wall in large scale integrated circuit logic device
  • Method for etching inclined shoulder type side wall in large scale integrated circuit logic device

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Embodiment Construction

[0019] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

[0020] The etching method of the sloping shoulder type sidewall in the VLSI logic device of the present invention comprises the following steps: Step 1, carry out lightly doped drain implantation process; Step 2, deposit dielectric film on gate (polysilicon), deposit first A layer of oxide film (SiO 2 ), and then deposit a layer of nitride film (SiN) (such as figure 1 shown); step 3, remove most of the dielectric film with plasma dry etching, and form sidewalls on the sides of the gate (such as figure 2 shown).

[0021] Since the etching of the side wall holes needs to etch the nitride film (SiN) and the oxide film (SiO) sequentially from top to bottom. 2 )(like figure 1 shown), so for films of different materials, corresponding etching conditions are used, and step 3 is specifically divided into the following two steps:

[0022] The f...

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Abstract

The invention discloses an etching method used for a shoulder-style side wall of a logic component of an ultra large scale integrated circuit, adopting a plasma-drying etching method to remove most of silicon oxide and silicon nitride medium films to form a side wall. The method includes the following steps: step A, main etching of top silicon nitride: adjusting electrode power, cavity pressure and flow proportion of reaction gases to raise isotropy etching trends so as to acquire an inclined top shoulder form of the side wall; step B, over-etching of silicon nitride: regulating proportions of fluoromethane and oxygen to get a high selection ratio of 16:1 to 22:1 between silicon nitride and silicon oxide. The invention adopts the method of raising the gradient of the top shoulder of the side wall to solve the problem of holes in the following PMD settlement process caused by the continuous reduction of the space between polysilicon grids so as to enhance the reliability of the component.

Description

technical field [0001] The invention relates to an integrated circuit semiconductor manufacturing process method, in particular to an etching method for oblique-shoulder sidewalls in a VLSI logic device. Background technique [0002] In a typical logic device process, after the lightly doped drain (LDD) implant process, it is necessary to make a dielectric spacer (Spacer) to surround the polysilicon gate to prevent a larger amount of source-drain implantation from being too close to the channel so that source-drain breakthrough may occur . [0003] The existing sidewall formation process is as follows: after the lightly doped drain implantation process, a layer of dielectric film is first deposited. At present, for different node processes, the type and number of layers of the dielectric film are different. Usually, first Deposit a thin layer of silicon oxide, then deposit a layer of silicon nitride, and then use plasma to perform reverse etching to remove most of the diele...

Claims

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Application Information

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IPC IPC(8): H01L21/311
Inventor 王函吕煜坤
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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