Method for analyzing and increasing yield of semi-conductor production line

Abstract

The invention discloses a method used for analyzing and improving yield of semiconductor production line. The invention is characterized in that a test chip is used for precisely determining the defect rate curves of various process modules of the production line and the failure rate of contact holes, and an effective area curve of power off, an effective area curve of leakage of each layer of product layout and the number of the contact holes are analyzed, and a model framework of the yield then can be built. The invention has the advantages that the invention can precisely calculate different effects of defect rates of various process modules on the yield and the invention enables production personnel to exactly know the effects of various process modules of the production line on the yield, thus the engineering personnel of the production line can be instructed to rapidly and effectively solve the deficiencies seriously affecting the yield, and the yield then can be improved rapidly and effectively.

Description

technical field [0001] The invention belongs to the field of integrated circuit manufacturing, in particular to a method for analyzing and improving the yield of integrated circuits. Background technique [0002] The yield rate of semiconductors and the speed of technology maturity determine whether a semiconductor manufacturer is profitable. How to improve the yield rate better and faster is an urgent problem to be solved. It is very important to establish an effective yield model and be able to quickly reduce fatal defects. Traditionally, the yield model uses the entire area of ​​the chip and the defect rate of each layer or each process module estimated from the optical measurement equipment to estimate the yield. The commonly used BOSE-EINSTEIN model is shown in formula (1). [0003] Y = Y s Π Layer 1 ( 1 + ...

AI Technical Summary

Problems solved by technology

From the above process, it can be seen that this assignment is more of an accumulation of experience, and there is no specific quantitative method, so it is impossible to accurately calculate the impact of each layer and a process module defect on the yield

[0006] 2) This yield model only considers the area of ​​the entire chip, and does not take into account the difference in layout design parameters

However, this setting is mostly based on experience, and it cannot be theoretically set accurately so that the equipment can detect all or most of the defects.

In addition, the sensitivity of defects in different materials is different; the sensitivity set for metal layer defects may not be applicable to oxide layers

This also greatly increases the difficulty of setting the effective sensitivity

[0009] 2) Not all measured defects are fatal defects

[0010] 3) The efficiency of defect measurement equipment is very low, and it takes a long time to measure a silicon wafer

The traditional test chip can only test part of the process defects, and many factors that affect the yield rate must rely on real products to test, which will greatly reduce the rate of improvement of the yield rate

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