Multi-chip stack packaging structure with asymmetric conductive wire rack

Abstract

The invention relates to a stacked chip packaging structure, comprising a wire rack, wherein, the wire rack comprises a plurality of internal pins and a plurality of external pins; the internal pins comprise a plurality of first parallel internal pin clusters and second parallel internal pin clusters, the tail ends of the first internal pin clusters and the second internal pin clusters are arranged oppositely with an interval; the tail ends of the first internal pin clusters and the tail ends of the second internal pin clusters have different vertical height due to the sink-arranged structure of the first internal pin clusters; the multi-chip stacked structure is connected fixedly with the first internal pin clusters; the metal welding points on the edge of the same side of the multi-chip stacking structure are connected electrically with the first internal pin clusters and the second internal pin clusters via a plurality of metal wires; the multi-chip stacked structure and the internal pins are packaged with sealant; and the packaging structure is provided with a top surface and a bottom surface.

Description

technical field [0001] The invention relates to a multi-chip stack packaging structure, in particular to a multi-chip stack packaging structure using lead frames with inner leads of different heights. Background technique [0002] In recent years, three-dimensional space (Three Dimension; 3D) packaging is being carried out in the back-end process of semiconductors, in order to achieve higher density or memory capacity with the least area. In order to achieve this goal, a chip stacked method has been developed to achieve a three-dimensional (Three Dimension; 3D) package at this stage. [0003] In the known technology, the chip stacking method is to stack multiple chips on the substrate, and then use a wire bonding process to connect the multiple chips to the substrate. Figure 1 discloses a structure of a chip stack package based on a lead frame, wherein Figure 1A for a cross-sectional diagram Figure 1B for Figure 1A floor plan. Such as Figure 1A As shown, the lead fram...

AI Technical Summary

Problems solved by technology

[0004] In the above-mentioned known chip stack package structure, since the metal wires 10, 11, 12 between each chip and the platform portion 5c of the lead frame 5 have different lengths and radians, the length and radian are not the same except during the sealing process. Longer metal wires are prone to displacement and lead to short circuit of the chip, but also because the lengths of the metal wires 10, 11, and 12 are not the same, resulting in changes in the phase of the electrical signal, etc.

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