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Method for producing compressive nitrifier layer and method for forming transistor

A technology of nitride layer and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to achieve the effect of increasing the contact window etching process window and improving the driving current gain

Active Publication Date: 2007-10-31
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, at a low temperature below 400°C by PECVD, the world's best coating (As-deposit) technology can only reach -1.6GPa

Method used

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  • Method for producing compressive nitrifier layer and method for forming transistor
  • Method for producing compressive nitrifier layer and method for forming transistor
  • Method for producing compressive nitrifier layer and method for forming transistor

Examples

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no. 1 example

[0045]A method for manufacturing a compressive nitride layer according to the first embodiment of the present invention may include performing a chemical vapor deposition process, such as PECVD, to form a nitride layer on the substrate. Moreover, a specific gas needs to be introduced during the chemical vapor deposition process, and this specific gas is selected from the group including argon (Ar), nitrogen (N 2 ), krypton (Kr) and xenon (Xe) or a combination thereof. For example, when the specific gas is a combination gas of argon and nitrogen, the flow rate of the argon gas is about 100 sccm-5000 sccm, and the flow rate of the nitrogen gas is about 1000 sccm-30000 sccm. In addition, the low frequency power (LF Power) used in the chemical vapor deposition process is preferably between about 50W-3000W.

[0046] Table 1 below is a table of process parameters for using the method of the first embodiment (experimental examples 1-2) and comparing with the traditional (comparative...

no. 2 example

[0053] 3A to 3D are schematic cross-sectional views of a process for forming a metal-oxide-semiconductor transistor according to a second embodiment of the present invention.

[0054] Referring to FIG. 3A , a substrate 300 is firstly provided, which may have a crystal orientation on the (100) crystal plane, and it is assumed that it can be divided into a PMOS region and an NMOS region by a plurality of isolation structures 302 . And the gate structure 304 has been formed on the substrate 300 . The gate structure 304 basically includes a gate dielectric layer, a gate located on the gate dielectric layer, and a spacer formed on the sidewall of the gate. In addition, it may also include other components, but because this belongs to the scope of the present invention A person skilled in the technical field can deduce it by relying on the existing technology, so details will not be described here.

[0055] Then, referring to FIG. 3B , a source and a drain 306 are formed in the su...

no. 3 example

[0060] 4A to 4D are schematic cross-sectional views of a process for forming a metal-oxide-semiconductor transistor according to a third embodiment of the present invention.

[0061] Referring to FIG. 4A , a substrate 400 is firstly provided, which can be a substrate having a crystal orientation on the (100) crystal plane, and it is assumed that it can be divided into a first region 400a and a second region 400b by a plurality of isolation structures 402 ; For example, when the first area 400a is a PMOS area, then the second area 400b is an NMOS area. Next, a gate structure 404 is formed on the substrate 400 in the first region 400a and the second region 400b respectively. Then, the source and drain 406 are formed in the substrate 400 on both sides of each gate structure 404 , and the method of forming the source and drain 406 can refer to the description of the second embodiment (see FIG. 3B ). Afterwards, a first buffer layer (buffer layer) 408 can be optionally formed on ...

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Abstract

A preparing method of compressibility nitride layer includes preceding a chemical gas phase aggradation to form a nitride layer on a base, it characterized in that definite gas is inlet into during the chemical gas phase aggradation, the definite gas is argon, nitrogen, krypton and xenon or their comnination. For adding said definite gas, the compress stress can be decreased, and the PMOS drive current plus is increased.

Description

technical field [0001] The present invention relates to a method for manufacturing a metal oxide semiconductor transistor, and in particular to a method for manufacturing a compressive nitride film and a method for forming a metal oxide semiconductor transistor (MOS). Background technique [0002] As the semiconductor process enters the deep sub-micron era, because increasing the drive current of NMOS and PMOS will greatly improve the time-delay performance of the transistor element, the process below 65nm will greatly improve the drive current of NMOS and PMOS. ) has become increasingly important. For example, traditionally there are researches on the development of low dielectric constant (low k) materials for ILD to increase the driving current. In recent years, domestic and foreign studies have begun to study the shallow trench isolation (STI) oxide layer, the silicon nitride (SiN) compression structure (stressor) of the polysilicon cap (Poly-Cap), and the silicon nitri...

Claims

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Application Information

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IPC IPC(8): H01L21/318H01L21/336H01L21/8238
Inventor 陈能国蔡腾群黄建中
Owner UNITED MICROELECTRONICS CORP
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