Semiconductor element and its producing method

Abstract

First, the method provides substrate. Cut line on the substrate divides the substrate into at least one chip. Being formed on the substrate, grooves are positioned on prearranged area, where weld pads are to be formed, or on the area between pads and the cut line. Low electrode is formed on sidewall of substrate, and in substrate of base. Dielectric layer of capacitance and up electrode are formed on the substrate. The up electrode is filled in the grooves. Then, being formed on the substrate, the doping area is connected to the low electrode electrically. Afterwards, first weld pad and second weld pad are formed on the substrate. Through the doping area, the low electrode is connected to the first weld pad electrically, and the up electrode is connected to the second weld pad electrically. Since capacitor is formed under pads, or on the substrate between pads and the cut line, the invention reduces area engaged by chip.

Description

technical field [0001] The invention relates to a semiconductor element and a manufacturing method thereof, in particular to a high-voltage semiconductor capacitor and a manufacturing method thereof. Background technique [0002] With the advancement of integrated circuit manufacturing, the size of components has been continuously reduced, and metal oxide semiconductor (MOS) has become the main component of circuit design. However, since the operating voltage of the MOS transistor is getting smaller and smaller, it is easy to be damaged due to the intrusion of external noise. Industry and academia have devoted a lot of effort to the prevention of noise, and many solutions have been obtained. [0003] When the input voltage is applied to the high-voltage components through the input pad (Input Pad), there will be similar noise problems. In order to stabilize the input voltage of the high-voltage component, a capacitor with a large capacitance (Capacitance) is arranged on th...

AI Technical Summary

Problems solved by technology

However, under the trend of increasing integration, the available chip area of ​​the capacitor plate (Plate) is forced to reduce, and the increasing function of active components makes the number of capacitors continue to increase. These problems are the application of MIM capacitors. bottleneck

Due to the current dielectric material and plate area available for MIM capacitors cannot provide sufficient capacitance (for example, 0.75fF / um is required for an input voltage of 18V 2 ) to deal with voltage regulation problems at higher input voltages

Therefore, there are obvious limitations in the way in which embedded MIM capacitors can be placed in order to stabilize the input voltage

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