Multi-channel high-speed data processor and processing method

Abstract

A method for processing multichannel high-speed data includes issuing read / write information and data information by network processor and obtaining said information by queue dispatch module, carrying out relevant write operation on buffer area by receiving module after it receives write command from queue dispatch module then sending processed data to frame calibration-sequence module and sending calibrated data to data buffer storage module, writing data in buffer area and outputting data by operating buffer area. The processor of multichannel high-speed data is also disclosed.

Description

technical field [0001] The device of the invention is a high-speed data processing device in the field of wireless network security, which uses a field programmable gate array (FPGA) as a basic platform, and is a multi-channel high-speed data processing system. Background technique [0002] The application of services such as high-speed packet data, multimedia data and Internet promotes the upgrade of Code Division Multiple Access (CDMA) from IS-95 to CDMA20001X. The International Organization for Standardization 3GPP2 has formulated the relevant standards of CDMA20001X packet data network, and adopted the existing work results of IETF in mobile IP technology, so that the network has the ability to quickly provide IP access, interoperability with other IP networks, and better Roaming capability and IP service capability of private network, and enable the system to provide 144Kbps, 384Kbps and 2Mbps access rate and simple IP and mobile IP service functions. [0003] In the C...

AI Technical Summary

Problems solved by technology

However, if this kind of work is completed by the network processor, it will increase the overhead of the system and greatly affect the performance of the system.

Images