Semiconductor packer and production for godown chip

Abstract

The semiconductor package consists of a chip carrier, a first chip connected to the chip carrier, multi heat sinks with through opening formed on the package and connected to the first chip and not touching the chip carrier, a second chip attaching to the heat sinks and connected to the chip carrier via the through opening, and a sealing colloid formed on the chip carrier and covering the first chip, second chip, wire and heat sinks. The invention integrates heat sink into semiconductor package to improve efficiency of heat dispersion of semiconductor chip.

Description

technical field [0001] The present invention relates to a semiconductor package with stacked chips and its manufacturing method, in particular to a semiconductor package with integrated heat sink and stacked chips and its manufacturing method. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually developing towards multi-functional and high-performance directions to meet the packaging requirements of high integration and miniaturization of semiconductor packages. In order to improve the performance and capacity of a single semiconductor package, in line with the trend of miniaturization, large capacity and high speed of electronic products, most of the existing products present the semiconductor package in the form of a multi-chip module (Multi Chip Module; MCM). This kind of package can reduce the volume of the whole package and improve the electrical function, so it becomes a mainstream of package. It is ...

AI Technical Summary

Problems solved by technology

[0009] However, in order to meet the light, thin, short, small, and high-function requirements of electronic products, the size requirements of semiconductor packaging structures are getting smaller and smaller. Therefore, chip-scale packaging (Chip Scale Package, SP) structures, such as thin ball grid arrays The demand for package (TFBGA) is increasing, but because the chip-scale package (CSP) semiconductor package emphasizes that the size of the substrate is equivalent to the size of the chip, and the area for chip wire bonding can only be formed in the area for chip bonding ( Die-Attaching Area) to the edge of the substrate, it is impossible to provide space for accommodating the support portion of the heat sink, so the heat sink with the support portion disclosed in the above-mentioned US Patent No. The extra space can be used to connect the support part of the heat sink, so that the heat sink cannot be applied in the CSP package structure or on the substrate with high-density wiring, and the setting of the support part of the heat sink in this process will also cause Difficulty in making substrates

[0010] In addition, in U.S. Patent No. 6,472,743, solder balls are provided at the corners of the substrate as the supporting portion of the heat sink, but this process involves changes in the structure of the substrate, and the height of the solder balls is difficult to control. The heat dissipation block on the chip is deflected, and even touches the signal wire of the chip to cause a short circuit, resulting in inconvenience in the process, a decrease in reliability and an increase in cost.

Moreover, in this process, in order to cooperate with the setting of the supporting part of the heat sink, it will also cause troubles in the production of the substrate.

[0011] Furthermore, in the above-mentioned semiconductor packages, since the bonding of the heat sink and the chip must be precisely controlled to avoid the occurrence of the tilt problem, the package of the semiconductor package cannot be bonded to the chip and the heat sink in a batch-type manner. ; That is, the heat sink must be bonded to the corresponding chips one by one, which increases the complexity of the overall packaging process and the required time schedule, so it is not conducive to the reduction of packaging costs and the improvement of packaging efficiency

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