ESD protection design with turn-on restraining method and structures

Abstract

The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I / O cell libraries. The ESD device according to the present invention uses a novel I / O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and / or varying channel lengths in the layout structure.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention is directed generally to electrostatic discharge (ESD) protection circuits for input / output (I / O) devices, and more particularly, to improving ESD robustness in I / O cell libraries using novel layout techniques to implement a turn-on retraining arrangement that reduces the turn-on speed or increases the breakdown voltage of a MOS transistor.[0003]2. Description of the Related Art[0004]The ESD robustness of CMOS integrated circuits (IC) has been found to be seriously degraded due to deep-submicron CMOS technologies. To improve the ESD robustness of the output transistors, the ESD-implant process and the silicide-blocking process have been widely implemented in the deep-submicron CMOS technologies. In addition to the process modification to improve the ESD robustness of the output buffers, the symmetrical layout structure had been emphasized to realize the large-dimension output transistors by ensurin...

AI Technical Summary

Benefits of technology

"The present invention provides a semiconductor structure for ESD protection of an integrated circuit to improve ESD level of different driving specifications. It includes a p-type substrate, first and second n-type channels, and an additional P+ pick-up diffusion region to reduce the turn-on speed of the first MOS transistor. The channel lengths of the first and second n-type channels can be varied to increase the drain breakdown voltage of the first MOS transistor. The semiconductor structure can be used to protect the internal circuit, output buffer, I / O buffer, input cell, or 3V / 5V-tolerant I / O cell library of the MOS integrated circuit by slowing down the turn-on speed or increasing the breakdown voltage of the output device with small driving current ability, such that the ESD-protection device with a large device dimension can be triggered on to bypass ESD current during an ESD stress event."

Problems solved by technology

The ESD robustness of CMOS integrated circuits (IC) has been found to be seriously degraded due to deep-submicron CMOS technologies.

This creates a challenge to provide one set of I / O cells with better ESD level.

Although such design methodology can improve the ESD level of the I / O library, it is costly and requires additional elements to realize the gate-coupled circuit or modifications to lower the junction breakdown voltage.

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