Sram cell fabrication with interlevel Dielectric planarization

Abstract

A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Description

[0001]This application is a continuation of application No. 08 / 328,736, filed Oct. 25, 1995, which was abandoned upon the filing herein which is a divisional of 08 / 49,338, filed Dec. 17, 1993, now U.S. Pat. No. 5,395,785.BACKGROUND AND SUMMARY OF THE INVENTION[0002]The present invention relates to integrated circuit fabrication methods and structures, and particularly to integrated circuits with minimum linewidths below one-half micron.[0003]Background: Planarization[0004]As the degree of integration has advanced, it has become increasingly apparently that it is desirable to minimize the topographical excursion of the surface at each level, especially the upper levels. To accomplish this, various planarization schemes have been used to planarize the inter-level dielectric. Some of these include Chemical-Mechanical-Polishing (CMP), use of Permanent Spin-on-glass (left in place in the final chip), and Sacrificial Etchback Spin-on-glass (SOG).[0005]Spin-on glass deposition is an exampl...

AI Technical Summary

Benefits of technology

The present invention is about making integrated circuits with very small lines. The technical effect is that this invention allows for the creation of more complex and efficient integrated circuits with smaller components.

Problems solved by technology

Unfortunately, the resistivity of such polysilicon is fairly variable, and an excessive value for the resistors may cause the cell to lose data under high-temperature conditions.

An excessively low value for the polysilicon resistor may lead to excess static power consumption.

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