Printability verification by progressive modeling accuracy

Abstract

A fast method of verifying a lithographic mask design is provided wherein catastrophic errors are identified by iteratively simulating and verifying images for the mask layout using progressively more accurate image models, including optical and resist models. Progressively accurate optical models include SOCS kernels that provide successively less influence. Corresponding resist models are constructed that may include only SOCS kernel terms corresponding to the optical model, or may include image trait terms of varying influence ranges. Errors associated with excessive light, such as bridging, side-lobe or SRAF printing errors, are preferably identified with bright field simulations, while errors associated with insufficient light, such as necking or line-end shortening overlay errors, are preferably identified with dark field simulations.

Description

BACKGROUND OF THE INVENTION[0001]This invention relates generally to the field of optical lithography, and more particularly, to a method for verifying the accuracy of the results of an Model Based Optical Proximity Correction (MBOPC) software tool for use in an optical lithography simulation, to provide accurate correction of the device shapes in a photo-mask that fulfill required performance criteria for the resulting Very Large Scale Integrated (VLSI) circuit.[0002]The optical micro-lithography process in semiconductor fabrication, also known as the photolithography process, consists of duplicating desired circuit patterns onto semiconductor wafers for an overall desired circuit performance. The desired circuit patterns are typically represented as opaque, complete and semi-transparent regions on a template commonly referred to as a photomask. In optical micro-lithography, patterns on the photo-mask template are projected onto the photo-resist coated wafer by way of optical imagi...

AI Technical Summary

Benefits of technology

[0009]Accordingly, it is an object of the present invention to provide a method for efficient computation of printability verification on a lithography layout.

[0010]It is another object of the present invention to progressively increase the accuracy of the printability verification simulation.

[0011]It is a further object of the present invention to provide a method to quickly prune out regions of the mask layout devoid of any errors.

Problems solved by technology

However, the ever shrinking device dimensions combined with the desire to enhance circuit performance in the deep sub-wavelength domain require complex OPC methodologies to ensure the fidelity of mask patterns on the printed wafer.

The ever increasing cost of mask manufacturing and inspection and the ever increasing complexity of OPC and RET require that the mask is correctly and accurately simulated for potential defects before the mask is manufactured.

The cost of finding the error when the mask is actually manufactured and is being used for chip manufacturing is extremely high.

Since, a missed error is significantly more expensive than a false error, all printability verification tools are expected to err on the conservative side.

If there are too many false errors, the real errors may be missed by the manual inspection and also it would require a lot of time to shift through all the false errors to find the real errors.

This tends to increase the runtime of the printability verification along with the number of false errors.

Furthermore, the goal of printability verification is to determine the existence of errors in printability, and identify such errors, rather than accurately determining what the image will look like.

However, it is also important that any real printability errors are not missed as a result of less accurate simulations.

Images