Semiconductor device with composite landing pad for metal plug

Abstract

The present disclosure relates to a semiconductor device with a composite landing pad. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate. The semiconductor device also includes a lower metal plug and a barrier layer disposed in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes an inner silicide portion disposed over the lower metal plug, and an outer silicide portion disposed over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion.

Description

TECHNICAL FIELD[0001]The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device with a composite landing pad.DISCUSSION OF THE BACKGROUND[0002]Semiconductor devices are essential for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming smaller in size while providing greater functionality and including greater amounts of integrated circuitry. Due to the miniaturized scale of semiconductor devices, various types and dimensions of semiconductor devices providing different functionalities are integrated and packaged into a single module. Furthermore, numerous manufacturing operations are implemented for integration of various types of semiconductor devices.[0003]However, the manufacturing and integration of semiconductor devices involve many complicated steps and operations. An increase in complexity of manufacturing and integration of the semiconductor device may cause deficiencies s...

AI Technical Summary

Benefits of technology

This patent describes a semiconductor device with improved performance and increased yield rate. The device includes a lower metal plug and a barrier layer, with an inner silicide and an outer silicide portion that creates a composite landing pad for an upper metal plug. This increases the landing area and reduces contact resistance, preventing misalignment issues between the lower and upper metal plugs. Overall, this design improves device performance and increases yield rate.

Problems solved by technology

However, the manufacturing and integration of semiconductor devices involve many complicated steps and operations.

An increase in complexity of manufacturing and integration of the semiconductor device may cause deficiencies such as misalignment in interconnect structures.

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