Clock buffer circuit of semiconductor device

Abstract

A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]The present application claims priority to Korean patent application number 10-2006-0138768, filed Dec. 29, 2006, which is incorporated by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor device, and more particularly to a clock buffer circuit for buffering a clock signal.[0003]In general, a semiconductor memory device, such as a dynamic random access memory (DRAM), comprises a memory array including a plurality of memory cells for storing data.[0004]Particularly, in a synchronous DRAM (SDRAM) among various DRAMs, a data read / write operation is carried out synchronously with an external clock signal. For this reason, in the SDRAM, there is a need for a clock buffer circuit to generate an internal clock signal which is in synchronization with the external clock signal.[0005]The clock buffer circuit for the SDRAM employs a differential amplifier to which a clock signal and an inver...

AI Technical Summary

Problems solved by technology

However, in a practical chip, the tR / tF characteristics may not be equal due to various external environmental factors, as shown in FIG. 3.

This means a duty distortion due to buffering, which leads to an increase in external parameters to be corrected by the DCC, resulting in a reduction in accuracy of the DCC.

As a result, this duty distortion deteriorates the high-speed operation of a memory device.

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