Semiconductor device and method for fabricating the same

Abstract

Into a channel formation region of a semiconductor substrate of p-type silicon, indium ions are implanted at an implantation energy of about 70 keV and a dose of about 5×1013 / cm2, thereby forming a p-doped channel layer. Next, germanium ions are implanted into the upper portion of the semiconductor substrate at an implantation energy of about 250 keV and a dose of about 1×1016 / cm2, thereby forming an amorphous layer in a region of the semiconductor substrate deeper than the p-doped channel layer.

Description

RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 10 / 676,877 filed Oct. 2, 2003, which is based on Japanese Patent Application No. JP 2002-297513, filed Oct. 10, 2002 the contents of which are hereby incorporated by reference in their entirety.BACKGROUND OF THE INVENTION [0002] The present invention relates to MIS semiconductor devices capable of accomplishing a further miniaturization and operating with high speed and low power consumption, and to methods for fabricating the same. [0003] With increasing packing density of a semiconductor device, MIS transistors in the device are requested to become miniaturized. To accomplish this request, a MIS transistor having a heavily-doped channel structure in which the dopant concentration of a channel region is made high is required (For example, Japanese Unexamined Patent Publication No. 08-250729). [0004] Hereinafter, a conventional method for fabricating a MIS transistor will be described wi...

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Benefits of technology

[0016] With the foregoing problems in mind, an object of the present invention is to ensure an increased dopant concentration of a dopant-diffused channel layer of a semiconductor device while the appearance of short channel effect accompanied with the miniaturization of the device is avoided, and to suppress an increase in leakage current flow resulting from a low threshold voltage and a highly doped channel of the device.

[0019] With the method for fabricating a semiconductor device of the present invention, the amorphous-crystal interface is moved down to the position in the substrate located deeper than that of the dopant implantation layer. Therefore, even if the subsequent thermal treatment is performed to restore the crystallinity of the substrate, no amorphous-crystal interface is formed in the dopant implantation layer. This eliminates the probability of occurrence of a dislocation loop defect layer in the dopant implantation layer during the thermal treatment after the heavy ion implantation, which prevents the phenomenon in which the heavy ions implanted in the channel formation region segregate to the dislocation loop defect layer to become inactivated. Moreover, since no dislocation loop defect layer is formed, leakage current flow resulting from the dislocation loop defect layer can be prevented as well.

[0020] It is known that even a relatively small dose of heavy ions generally amorphizes part of a semiconductor substrate because of their mass effect. In the present invention, the amorphous-crystal interface is expanded deeper than the channel formation region. Therefore, even though the heavy ions are implanted into the channel formation region at a higher dose than the extent that the ions induce amorphization of the region, the heavy ions cause no dislocation loop defect layer immediately below the channel formation region during the thermal treatment after the implantation. This suppresses segregation of the heavy ions immediately below the channel formation region, thereby attaining a heavily-doped and abrupt channel formation region with a retrograde profile.

[0030] Preferably, the inventive method further comprises, between the second and third steps, the step of performing a third thermal treatment at such a temperature that the first dopant ions do not diffuse from the dopant implantation layer and that the crystallinity of the amorphous layer is restored, thereby recovering crystal damages caused by the first dopant ions.

[0031] This method restores the crystallinity of the semiconductor substrate with implantation damages introduced by the heavy ion implantation in the first step while the occurrence of residual defects is prevented.

Problems solved by technology

As a result, the conventional method cannot provide a transistor having a desired dopant profile.

Moreover, if the dislocation loop defect layers are formed in the p-diffused channel layer 203, leakage current disadvantageously flows along the dislocation loop defect layers.

As is apparent from the above, it is difficult for the conventional method for fabricating a semiconductor device to form a heavily-diffused channel layer, which is dispensable for a miniaturized transistor, to have a desired dopant concentration.

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