SOI CMOS device with reduced DIBL

Abstract

CMOS devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant through openings in a masking layer and through channel regions of the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) diffusion source within the insulation layer underlying the gate regions of the SOI wafer substantially between the source and drain. Backend, high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the p- and n-wells, thereby forming asymmetric retrograde dopant profiles in the channel under the gate. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

Description

RELATED APPLICATIONS [0001] This application is a continuation of U.S. application Ser. No. 10 / 801993 filed Mar. 16, 2004 which issued (issue date unknown) as U.S. patent (patent number unknown).BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to the field of semiconductor devices and fabrication processes and, in particular, to CMOS devices formed in a silicon-on-insulator (SOI) technology with improved avoidance of short channel effects, such as reduced drain induced barrier lowering (DIBL) and a method for fabricating the same, including arrays of memory cells with peripheral logic circuits. [0004] 2. Description of the Related Art [0005] There is an ever-present desire in the semiconductor fabrication industry to achieve individual devices with smaller physical dimensions. Reducing the dimensions of devices is referred to as scaling. Scaling is desirable in order to increase the number of individual devices that can be placed on a given a...

AI Technical Summary

Benefits of technology

This approach effectively reduces DIBL, improves device reliability, and maintains desired device characteristics by creating retrograde dopant profiles that inhibit drain-induced barrier lowering, reduce junction capacitances, and enhance circuit speed without requiring significant additional processing steps or high temperature processing.

Problems solved by technology

However, scaling often creates some performance drawbacks.

In particular, a known category of performance limitations known as short channel effects arise as the length of the channel of CMOS devices is reduced by scaling.

When the drain voltage is increased, the depletion region around the drain increases and the drain region electric field reduces the channel potential barrier which results in an increased off-state or leakage current between the source and drain.

However in some applications, such as in an SOI process, it is difficult to create a retrograde profile due to the thinness of the silicon layer and the tendency of the dopants to diffuse.

One difficulty encountered in SOI processes is that increasing the Si film thickness to facilitate forming a retrograde profile will increase the extent to which the devices formed therein get partially depleted.

SOI devices also suffer from ‘floating body’ effects since, unlike conventional CMOS, in SOI there is no known easy way to form a contact to the bulk in order to remove the bulk charges.

Another difficulty is that when as-implanted retrograde dopant profiles diffuse during subsequent heat cycles in a process, they tend to spread out and lose their ‘retrograde’ nature to some extent.

In SOI, since the silicon film is very thin, creating and maintaining a true retrograde dopant profile is very difficult.

As CMOS devices are scaled ever smaller, balancing the threshold voltage and drive currents between the PMOS and NMOS devices which employ different doping species becomes increasingly challenging.

There is also a challenge in obtaining desired device characteristics with aggressively scaled memory arrays, for example, where a portion comprises memory device circuits and a portion comprises interface logic circuits.

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