Driving chip packaging structure engaged by multilayer lug and driving chip

Abstract

This invention relates to drive chip seal structure and drive chip by use of multiple layer of protruding block, which comprises one circuit film and one drive chip, wherein, the film conductor circuit layer has multiple connection terminal; the drive chip has one active surface to form multiple weld pads and protruding blocks set on the main surface of chip to supply thermal binding bench connection terminals; each multiple protruding blocks comprise one basic metal layer and one binding metal layer.

Description

technical field [0001] The invention relates to a driving chip packaging structure, in particular to a driving chip packaging structure utilizing multi-layer bump bonding and a driving chip with multi-layer bumps. Background technique [0002] The conventional driver chip packaging structure includes Tape Carrier Package (TCP) or Chip On Film (COF), in which gold bumps are first formed on the pads of the driver chip, and then Thermal compression bonding to tape or film, and during the packaging process, because the hardness value of the gold bump changes too much, the process parameters must be controlled within a small range, that is, the process window (process window) ) is small, and the hardness value of the existing conventional gold bump is between Vickers hardness (Hv) 35 to 65, that is, the variation range is Vickers hardness 30, and the allowable inner lead bond (ILB) The parameter changes are small. [0003] A known bump structure is as disclosed in Taiwan Patent...

AI Technical Summary

Problems solved by technology

[0003] A known bump structure is as disclosed in Taiwan Patent Announcement No. 488052 "Process of Forming Metal Bumps with More than Two Layers by Electroless Plating". Inner metal bumps, the material of the inner metal bumps is nickel, and its height is more than 15 μm, and a peripheral metal layer made of gold completely covers the outer periphery of the inner metal bumps, so that the double layer The total thickness of the above metal bumps is more than 18μm. After the bumps are formed on a plurality of solder pads of a chip, the wafer test step must be performed. During the wafer test process, the probes must be inserted into these solder pads. For the metal bumps with more than two layers on the pad, because the height of the peripheral metal layer (gold) is less than one-fifth of the inner layer metal bump (nickel), that is, the thickness of the gold layer is thinner, and the probe will be easily pierced. Penetrating the gold layer and touching the harder nickel layer makes the probe easy to wear. In severe cases, even the thickness of the gold layer is too thin, so that the material of the entire bump is too hard and the probe cannot be inserted into the bump. For wafer testing, in addition, since the thermal compression bonding between the bump and the inner lead is to use gold and the tin plated on the inner lead to produce eutectic (eutectic) bonding, if the thickness of the gold layer of the metal bump with more than two layers If it is too thin, it will make the eutectic poor and affect the strength of the inner pin joint

[0004] It can be seen that the above-mentioned existing driver chip packaging structure obviously still has inconvenience and defects in structure and use, and needs to be further improved urgently.

In order to solve the problems existing in the packaging structure of the driver chip, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable structure for general products to solve the above problems. Obviously, it is a problem that relevant industry players are eager to solve.

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