Information processing device, interrupt processing control method, and computer program

A technology of information processing equipment and state information, which is applied in the field of computer programs, can solve the problems of reducing system efficiency, etc., and achieve the effects of reducing shielding time, effective data processing, and improving interrupt response

Inactive Publication Date: 2007-01-31
SONY GRP CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

As the interrupt masking period is extended, the overall system efficiency is reduced

Method used

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  • Information processing device, interrupt processing control method, and computer program
  • Information processing device, interrupt processing control method, and computer program
  • Information processing device, interrupt processing control method, and computer program

Examples

Experimental program
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Embodiment Construction

[0055] In the following, an information processing device, an interrupt process control method, and a computer program according to embodiments of the present invention are described by referring to the drawings.

[0056] Below, by referring to figure 1 The hardware structure of an information processing device of one embodiment of the present invention is described. The processor module 101 includes a plurality of processing units, and processes data according to various programs (including an operating system (OS) and application programs running on the OS) stored in a read only memory (ROM) 104 and an HDD 123 . later by reference figure 2 Processor module 101 is described.

[0057] In response to commands input via the processor module 101 , for example, the graphics engine 102 generates data to be displayed on a screen forming a display of the output unit 122 , performing a 3D drawing process. A main memory (DRAM) 103 stores programs executed by the processor module 10...

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PUM

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Abstract

There is provided an improved interrupt processing control configuration in a system where a plurality of operation systems (OS) are simultaneously operating. In the system where a plurality of OS are simultaneously operating, a main OS to execute an interrupt processing control is set and no interrupt mask setting authority is given to a sub-OS other than the main OS. The sub-OS reports whether the sub-OS is in an interrupt-enabled state or an interrupt-inhibited state to the main OS. According to the reported information, the main OS performs an interrupt mask control of the sub-OS. With this configuration, it is possible to eliminate the problem of reservation of the interrupt processing by the mask control of the sub-OS itself and perform an interrupt control based on the intention of the main OS. A necessary interrupt processing can be performed with a higher priority. Moreover, since the main OS manages the sub-OS interrupt vector area, it is possible to realize memory area reduction.

Description

technical field [0001] The present invention relates to an information processing device, an interrupt process control method, and a computer program. More specifically, the present invention relates to an information processing device, an interrupt control method, and a computer program for setting a main operating system (OS) for controlling interrupt processes in a system including a plurality of OSs so as to reduce the overall System interrupt mask (mask) time, improve interrupt response, and achieve efficient data processing. Background technique [0002] In a multi-operating system (OS) having a plurality of OSs in a single system, each OS can execute a corresponding process, and successively switch system-common hardware such as a central processing unit (CPU) and a memory in a time-series manner. [0003] For example, scheduling of processes (tasks) of a plurality of OSs is performed by a partition management software program. If OS(α) and OS(β) coexist in a single...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48G06F9/46
CPCG06F9/4812
Inventor 沖野直人户川敦之
Owner SONY GRP CORP
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