Access buffer storaging method

Abstract

This invention discloses a kind of method for accessing buffer store. Through arranging n buffer cells, write clock identification signal which cycle is n times write clock cycle and read clock identification signal which cycle is n times read clock cycle on the first-in first-out buffer, all the buffer cells are undertaken write operation successively during write clock signal cycle. When writing the first buffer cell, the write clock signal is high level, the others are low level; the write clock identification signals are sampled during the rising edge of each write clock cycle, which is in the write clock identification signal cycle. The rising edge position of the write clock identification signal is decided according to the sampled consequence; the buffer cells are began to undertaken read operation from at least the second read clock cycle after the write clock cycle corresponded to the rising edge of write clock identification signal. This method can ensure that the delay error does not exceed clock jittering range. The designing complexity of logical circuit is decreased.

Description

technical field [0001] The present invention relates to cache, in particular to a method for accessing cache. Background technique [0002] In many fields such as 3G mobile communication base stations, the delay accuracy requirements of signals in hardware are often very strict. For example, in the 3GPP protocol specification of the WCDMA (Wide-band Code Division Multiple Access, wideband code division multiple access) system, it is required that the relative delay error between the signals on the two antennas of the transmit diversity should not exceed 1 / 4 chip (approximately 65ns), Another example is in the CPRI (Common Public Radio Interface, common public radio interface) protocol, requiring REC (Radio Equipment Control, radio frequency equipment controller) equipment to RE (Radio Equipment, radio frequency equipment) equipment hardware interface delay accuracy better than 1 / 32chip (approximately 8ns). This not only has high requirements on the delay consistency of an...

AI Technical Summary

Problems solved by technology

[0011] The purpose of the present invention is to provide a method for accessing the buffer to solve the problem of uncertain delay error of the first-in-first-out buffer due to clock jitter when data transmission is performed between two boards with no relative frequency difference between the receiving and sending clocks. Using this method can ensure that the delay error of the FIFO does not exceed the jitter range of the clock, and at the same time reduce the design complexity of the logic circuit of the FIFO

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