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Clock phase-locked loop and clock phase-locking control method

A control method and phase-locked loop technology, applied in the field of network synchronization, can solve the problems of unweakened jitter and drift, poor clock synchronization effect, etc., and achieve the effect of flexible control and improved control accuracy

Active Publication Date: 2006-05-10
DATANG MOBILE COMM EQUIP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0011] The purpose of the present invention is to provide a clock phase-locked control method and a clock phase-locked loop to solve the technical problem that the prior art does not weaken and filter the jitter and drift of the reference clock signal, resulting in poor clock synchronization effect

Method used

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  • Clock phase-locked loop and clock phase-locking control method
  • Clock phase-locked loop and clock phase-locking control method
  • Clock phase-locked loop and clock phase-locking control method

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Embodiment Construction

[0037] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0038] see figure 2, which is a structural schematic diagram of the phase-locked loop of the present invention. It includes phase detector 11, pre-filter 17, loop filter 12, D / A converter 13, crystal oscillator 14, frequency divider 15 and processor 16, wherein:

[0039] The phase detector 11 is connected to the frequency divider 15 and the pre-filter 17, and its input is used to receive the clock signal of the crystal oscillator 14 after frequency division by the frequency divider 15 and the clock signal input by the reference clock source, and its output Connect the pre-filter 17 for outputting the phase difference of the two clock signals;

[0040] In fact, the phase detector 11 is a counter-based phase comparison device for detecting the phase difference between the reference clock signal and the output signal of the crystal oscillator 14 . The phase detector...

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Abstract

This invention discloses one time lock phase loop and its control method, wherein, the time phase loop comprises the following parts: phase test device, loop filter, D / A converter, transistor resonance and frequency division device phase negative feedback loop and the processor connected to the loop and the front filter set between the test and loop filter, wherein, the said filter is connected to the processor to receive and store several phase difference from the pre-set update circle and to filter out phase difference from the shaken or floating signal of reference time to improve the clock phase loop control accuracy.

Description

technical field [0001] The invention relates to network synchronization technology, in particular to a clock phase-locked loop and a clock phase-locked control method. Background technique [0002] In order to ensure the normal operation of the communication network, the network synchronization technology is usually used to strictly control the clock frequency and phase of all nodes in the communication network within a certain tolerance range. Network synchronization technology is mainly divided into two categories: quasi-synchronous method and synchronous method. The quasi-synchronous technology is often used in international links. Each node independently sets a reference clock, and its frequency accuracy is kept within a very narrow frequency tolerance. . Domestic communication networks in various countries generally adopt master-slave synchronization technology. What is master-slave synchronization technology? That is, all the clocks in the communication network are ...

Claims

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Application Information

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IPC IPC(8): H03L7/093H03L7/06H04L7/00
Inventor 刘飚
Owner DATANG MOBILE COMM EQUIP CO LTD
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