Static discharge protecting method for full chip

Abstract

This invention relates to one total chip static discharge protective method and the chip in near circle property distance comprises one ringed first metal layer and second metal layer, which forms first conductor base material reversed second conductor below first metal layer to form one large memory tank capacity through near circle ringed second conductor to achieve memory and discharging function. Through the method it adds total chip protective ability on static electricity without altering original integration circuit design and process and extra area.

Description

technical field [0001] The invention relates to a full-chip electrostatic discharge protection method, in particular to a full-chip electrostatic discharge protection method without changing the design and manufacturing process of the original integrated circuit, and without additionally increasing the area of ​​the full-chip electrostatic discharge protection method. Background technique [0002] Integrated circuit (IC) chips, with the evolution of the manufacturing process, the size of the components has been reduced to the deep-submicron (deep-submicron) stage, in order to improve the performance and operation speed of the integrated circuit, and reduce the manufacturing cost of each chip. However, with the shrinking of the component size, some reliability problems appear, such as electrostatic discharge (Electrostatic Discharge; ESD). [0003] According to the causes of ESD and the different ways of discharging integrated circuits, ESD is currently divided into the foll...

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Problems solved by technology

It can be seen that even if the size of the component remains the same, the ESD protection capability of the component will drop significantly due to the advanced manufacturing process; even if the size of the component is increased, the ESD withstand voltage does not necessarily increase proportionally. The layout area occupied by the large relative ground will also increase, and the size of the entire chip will also increase, but the ability to withstand electrostatic discharge will be seriously reduced. Many deep sub-micron CMOS integrated circuit products are facing this thorny problem.

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