Stacked semiconductor device and semiconductor chip control method

Abstract

Each of stacked memory chips has an ID generator circuit for generating identification information in accordance with its manufacturing process. Since the memory chip manufacturing process implies process variations, the IDs generated by the respective ID generator circuits are different from one another even though the ID generator circuits are identical in design. A memory controller instructs an ID detector circuit to detect the IDs of the respective memory chips, and individually controls the respective memory chips based on the detected IDs.

Description

technical field [0001] The present invention relates to a semiconductor device and a control method of a semiconductor chip, and more particularly to a stacked semiconductor device having semiconductor chips such as memory chips stacked one on top of another, and a method of controlling the semiconductor chip. Background technique [0002] It is foreseeable that if semiconductor manufacturing processes encounter difficulties in miniaturization in the future, increases in chip size associated with improvements in the functions of LSI chips (for example, increased storage capacity of DRAM) cannot be avoided by process-based miniaturization. [0003] In order to solve this possible problem, it is proposed that semiconductor devices (for example, DRAM) adopt a CoC (Chip on Chip) structure, which may include one layer stacked on another for the three-dimensional expansion function of the LSI chip (for example, the storage capacity of DRAM). An LSI chip on one. [0004] Currently...

AI Technical Summary

Problems solved by technology

This leads to an increase in manufacturing steps

[0025] On the other hand, a complex manufacturing process

Disadvantageously, this will lead to an increase in manufacturing cost

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