Method and equipment of pipeline treating series treatment command

A technology for processing instructions and pipelines, applied in the direction of concurrent instruction execution, electrical digital data processing, memory systems, etc., can solve problems such as unavailability, and achieve the effect of improving efficiency

Inactive Publication Date: 2004-10-06
THOMSON LICENSING SA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, said results are not available as long as the flag is set

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  • Method and equipment of pipeline treating series treatment command
  • Method and equipment of pipeline treating series treatment command

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Embodiment Construction

[0027] exist figure 1 , the (sequential) instruction stream enters the first stage STG0 of a series of n pipeline processing stages STG0 to STGN-1. Each of these stages includes, for example, a series of registers and appropriate processing means that perform typical calculations or operations performed in a CPU or microprocessor. For example, stages STG3 to STGn-2 can forward intermediate or partial results to the forwarding bus FWDB, or to a multiplexing bus. However, depending on the application, stages STG2 and / or STG1, or otherwise subsequent stages STG4, STG5, . . . , may also not forward intermediate or partial results to the FWDB bus. Stages STG0 to STGn-2 are capable of forwarding intermediate pipeline processing results to corresponding subsequent stages for further processing. The first stage STG0 is able to read intermediate or partial results from the bus FWDB and / or from the register file REGF. The final stage STGn-1 writes the final result into the register f...

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Abstract

Processor instruction pipelines, which split the processing of individual instructions into several sub-stages and thus reduce the complexity of each stage while simultaneously increasing the clock speed, are typical features of RISC architectures. Operands required by the processing are read from a register file. Read-after-write access problems in the pipeline processing can be avoided by using a scoreboard that has an individual entry per address of the register file. Once an instruction enters the pipeline, a flag is set at the address of the destination address of this particular instruction. This flag signals that an instruction inside the pipeline wants to write its result to the respective register address. Hence the result is unavailable as long as the flag is set. It is cleared after the instruction process has successfully written the result into the register file. According to the invention, not only a single flag but the number of the pipeline stage, which currently carries the instruction that wants to write its result to a particular register file address, and the type of the respective instruction is stored in the corresponding scoreboard address for the particular instruction.

Description

technical field [0001] The present invention relates to a method and apparatus for pipelining a sequence of processing instructions, and more particularly to forwarding instruction schedules and results for Reduced Instruction Set Computer (RISC) architecture logic. Background technique [0002] Processor instruction pipelining, which divides the processing of a single instruction into several (sub)stages and reduces the complexity of each stage while increasing clock speed, is typical of Reduced Instruction Set Computer (RISC) architectures. Such a pipeline has the ability to process one instruction per cycle, but each instruction has a latency of a few or "n" cycles. This situation leads to two conclusions that are relevant to the present invention: A) If a particular instruction in a continuous instruction stream produces a result that it needs as an operand for one or more instructions of its immediate successor, the processing of that successor instruction must wait ( ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3836G06F9/3838G06F9/38
Inventor 延斯·维滕贝格蒂姆·尼格迈尔
Owner THOMSON LICENSING SA
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