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Message storing method for wide-band digital communication chip

A data communication and message technology, applied in the field of chips, can solve problems such as threats to system reliability and stability, increased system complexity, and difficulty in use, and achieve the effects of reducing resource consumption, increasing stability, and saving logic volume

Inactive Publication Date: 2004-09-08
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the addresses of these wasted storage units are discontinuous in the entire storage area and appear in the form of fragments, it is very difficult to use them directly, which not only causes very troublesome addressing, but also costs more The savings lead to an increase in the complexity of the entire system, which threatens the reliability and stability of the system
Obviously, it is not advisable to expand the storage area size at the expense of system reliability and stability

Method used

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  • Message storing method for wide-band digital communication chip
  • Message storing method for wide-band digital communication chip
  • Message storing method for wide-band digital communication chip

Examples

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Embodiment Construction

[0023] 2 for a buffer n Byte storage area, the addressing space is 0~2 n -1 unit (take the bit width of 8 as an example), after partitioning in units of 2048 bytes, the addressing address of each data unit can be divided into two parts: base address (high address) and offset address (low address) Composition, where the range of the base address is related to the size of the storage area, which is 0~2 n-11 -1; the range of the offset address is related to the size of the partition, here is 2048 bytes, so the addressing range is 0~2 11 -1, that is, 0x000~0x7FF. Since the Ethernet message is limited to a maximum of 1536 bytes, the actual use range of the offset address is 0x000~0x5FF, and the units 0x600~0x7FF are wasted space, a total of 512 units. Throughout the buffer, all wasted units are fragmented:

[0024] Base address Offset address Physical address (HEX) Physical address (BIN)

[0025] 0x000 0x600~0x7FF 0x00600~0x007FF 0000-0000-0 11 0-0000-0000~0000-0000-0 11 1-1...

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Abstract

The message storing method for wide-band digital communication chip includes the following steps: defining the width of logic address and the physical address, with the logic address being one bit wider than the physical address; sectioning the memory region of the physical address in 2048 bytes each and addressing in the basic address plus offset, with the addressing space of the offset being within 1536 bytes; setting the lower 1536 bytes of each sections as message storing area and the rest 512 bytes as extended memory area; defining the MSB 0 / 1 as logic address addressing range of corresponding message storing area and MSB 1 / 0 as logic address addressing range of corresponding extended memory area; and establishing the mapping mechanism between the logic address and the physical address to realize the continuity of memory units, basic addresses and offset of the extended memory area addresses. The present invention raises the utilization of the memory space.

Description

Technical field: [0001] The invention relates to the field of chip technology, in particular to a storage method for a broadband data communication chip. Background technique: [0002] With the rapid development of local area networks, ethernet has become the most widely used networking method at present. The transmission bandwidth of Ethernet has also developed from 10M Ethernet to 100M Ethernet, Gigabit Ethernet and 10G Ethernet. [0003] It is impossible to process Ethernet packets with such a large bandwidth without the support of hardware forwarding chips. Massive data, such high bandwidth, and complex processing tasks also put forward high requirements on the performance of the chip, not only requiring the chip to have a large forwarding bandwidth, but also to have a good traffic scheduling capability, otherwise the packet will be blocked , message burst and other issues will greatly reduce the forwarding performance of the chip, and the flow scheduling capability of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/06
Inventor 龙刚
Owner HUAWEI TECH CO LTD
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