Interconnection structure containing stress regulating covering and its mfg. method

Abstract

Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.

Description

technical field [0001] The present invention relates generally to integrated circuits (ICs), and more particularly to interconnect structures, including multilayer interconnect structures, in which the internal stress of the structure is substantially reduced through the use of a stress regulating capping layer. The invention also relates to a method of fabricating an interconnect structure with greatly reduced internal stress. Background technique [0002] Typically, a semiconductor device includes multiple circuits forming an integrated circuit, including a chip (eg, a chip back end of line, or "BEOL"), a thin film package, and a printed circuit board. Integrated circuits are used in computers and electronic equipment and can contain millions of transistors and other circuit elements fabricated on a single crystal silicon substrate. In order for the device to work, a complex network of signal paths is usually provided to connect circuit elements distributed over the surfa...

AI Technical Summary

Problems solved by technology

[0005] Another problem associated with these existing structures is the poor adhesion observed at the location of the interface of the uppermost narrow line layer and the lowermost wide line layer

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