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High speed data link control protocol receiving processing module and data processing/method

A link control protocol and high-speed data technology, applied to electrical components, transmission systems, etc., can solve problems such as large chip area and ineffective increase in port speed, and achieve the effect of improving processing capacity

Inactive Publication Date: 2004-01-07
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

The arbitration in these places becomes the bottleneck of the system speed, so even if the speed of each processor is increased, the port rate cannot be effectively improved
Using this scheme, when the main clock is 33MHz, the maximum port rate of each port can only reach about 8Mbps at most, and since 16 receiving HDLC protocol processors are used, the occupied chip area is also large

Method used

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  • High speed data link control protocol receiving processing module and data processing/method
  • High speed data link control protocol receiving processing module and data processing/method
  • High speed data link control protocol receiving processing module and data processing/method

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Embodiment Construction

[0038] A kind of HDLC protocol receiving processing module and data processing method thereof for controlling the serial port communication controller chip of N (taking N=16 as embodiment) ports that the present invention proposes, in conjunction with accompanying drawing, describe in detail as follows:

[0039] The HDLC protocol receiving processing module structure of the present embodiment is as shown in Figure 5, and it is made up of a port arbitration module, a receiving HDLC protocol processor and a state memory module; Wherein, the input end of the port arbitration module is connected with 16 ports simultaneously Connection, the input end of the receiving HDLC protocol processor is connected to the output end of the port arbitration module, and is connected to the state memory module bidirectionally at the same time, the output end of the receiving HDLC protocol processor is connected to the input end of the first-in-first-out buffer (FIFO) of the subsequent circuit .

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Abstract

This invention relates to a HDLC protocol receiving process module and its data process method, in which, the module is composed of a port arbitration module, a receiving HDLC protocol processor and a module of state memory. The data process method is that N-port shared data process pipelines provide arbitration to the port arbitration module and send data to be processed to the receiving HDLC protocol processor orderly according to priorities which reads out the state data of its belonged HDLC channel from the state memory module to be processed in pipeline and write back the new state data to the memory. Using one parallel HDLC protocol receiving processor to process all port data streams.

Description

technical field [0001] The invention belongs to the technical field of network interconnection equipment, and in particular relates to the structural design of a high-speed data link control (HDLC) protocol receiving and processing module and its data processing method. Background technique [0002] Serial communication control chips are usually used in communication devices such as routers and switches, and often need to control multi-port and multi-channel data streams at the same time, which means performing high-speed data links on multiple channels of multiple ports at the same time. Send / receive processing of the HDLC protocol. [0003] The HDLC protocol is at the second layer of the Open Systems Interconnection (OSI) seven-layer network reference model: the data link layer. The data frame structure of the HDLC protocol is shown in Figure 1. In the figure: the HDLC data frame uses the hexadecimal number 7E (0x7E) as the frame start and frame end signs, and there is a ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/08
Inventor 黄勇张赞
Owner HUAWEI TECH CO LTD
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