Low power dissipation group associated cache memory adopting improved time sequency

Abstract

The invention is a kind of low-power consumption high-speed cache which is controlled by the improved sequence. The load operation sequence adopts that it reads each tag sarum but does not read the data sram, after that the result of tag comparator is reads the selected data scram (when cache is selected) or does not read any data sram (when cache is useless). The circuit of the invention is madeup of tag sram, data sram, tag comparator, data output multiplexer and drive circuit. The power consumption of the cache is low than conventional cache.

Description

technical field [0001] The invention relates to a low power consumption multi-way set associative cache memory (cache) designed with improved timing control. Background technique [0002] The design of low-power Cache is a bottleneck in the design of low-power processors. Since the power consumption of the cache usually accounts for a considerable part of the power consumption of the entire processor (accounting for about 20% to 50% depending on the processor and the size of the Cache), designing a low-power cache is helpful for improving processor performance and reducing the overall processor performance. The power consumption of the processor is extremely critical. Especially in recent years, the popularity of mobile electronic devices and personal communication devices (such as notebook computers and cellular phones) has made these circuit systems more urgent for low-power processors, so the design of low-power cache is extremely necessary. [0003] High-speed cache or...

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Problems solved by technology

But the shortcoming of this kind of Cache is also obvious: firstly, the hardware circuit complexity increases greatly, need to increase the hardware circuit of look-up table (look-up table); The key parameter of the processor's maximum operating frequency) is more than 60% higher than the traditional data parallel read cache, and even in the case of a cache miss, it will still read a data sram, wasting the read of the data sram power consumption

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