Nonvolatile memory for catching charges in isolative films

Abstract

Dummy cells in an erased state and in a write state are used to generate a dummy current corresponding to the average current of currents flowing in the dummy cells using a 1 / 2 current generating circuit, and the dummy current is compared with a current corresponding to a memory cell current flowing in a selected normal cell using a current sense amplification circuit to generate internal read data according to a result of the comparison. With such a configuration, a non-volatile semiconductor memory device capable of reading data at high speed can be achieved.

Description

[technical field] [0001] The present invention relates to a nonvolatile semiconductor memory, and more particularly to a structure for high-speed readout of data in a nonvolatile semiconductor memory. More specifically, the present invention relates to a data readout structure for a nonvolatile semiconductor memory having an insulating film charge trap type memory cell that stores charges in an insulating film. [Background technique] [0002] As a memory that stores information in a non-volatile manner, a bulk-erasable EEPROM (read-only memory that can be electrically written / erased) has memory cells formed of stacked gate field effect transistors. In this bulk-erase EEPROM, charges are stored in a floating gate insulated from its surroundings, for example, made of polysilicon, and the threshold voltage of a memory cell transistor is changed according to the amount of stored charges to store information. [0003] In the case of a nonvolatile memory cell structure using this...

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Problems solved by technology

[0042] However, the current flowing through the memory cell MC is on the order of μA. Therefore, in order to accurately read data with a sufficient margin, the time until time t0, that is, the charging time of the capacitive element 921 must be sufficiently long.

In this way, its read data cannot be generated at high speed, resulting in the problem that high-speed access cannot be realized.

[0043] In particular, in the case of selecting a 1-bit memory cell, continuously reading the 2-bit data stored in the 1-bit memory cell internally, and reading it to the outside in parallel, it is impossible to read data at a high speed. The problem with multivalued data like this

[0044] At the time of reading the data, in the configuration in which the capacitive element 921 is precharged to a predetermined voltage level and a current is supplied to the selected bit line according to the charged voltage of the capacitive element 921, similarly, in the programming state and the erasing state, In the memory cell, in order to give a sufficient difference in the charging voltage level of the capacitive element, it is necessary to delay the activation of the amplifier circuit 922, resulting in the same problem

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