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Double-chip stacked packaging structure and method

A packaging structure and packaging method technology, applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of small product capacity, low single-chip efficiency, etc., to increase product capacity, increase production, and save stacking effect of space

Pending Publication Date: 2022-07-29
华天科技(南京)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide a double-chip stack packaging structure and method to solve the problem of single-chip scribing, single-chip grasping and stacking, and single-chip packaging in the prior art. Low, the problem of small product capacity

Method used

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  • Double-chip stacked packaging structure and method
  • Double-chip stacked packaging structure and method

Examples

Experimental program
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Embodiment approach

[0031] like image 3 As shown, it is a single-chip stacking package structure in the prior art, including: the first chip 1 is fixed on the substrate 6 through the first adhesive film 5; the second chip 2 is fixed on the first chip 1 through the first adhesive film 5; The three chips 3 are fixed on the second chip 2 by the first adhesive film 5; the second chip 4 is fixed on the third chip 3 by the first adhesive film 5; the first chip 1 and the substrate 6 are electrically connected by the gold wires 7; The second chip 2 and the first chip 1 are electrically connected through the gold wire 7 ; the third chip 3 and the second chip 2 are electrically connected through the gold wire 7 ; the fourth chip 4 and the third chip 3 are electrically connected through the gold wire 7 .

[0032] like Figure 4 As shown, it is a single-chip stack packaging method in the prior art, including:

[0033] Scribing process: After the wafer 11 is supplied, the wafer 11 is diced to form a dicin...

Embodiment 1

[0038] like figure 1 As shown, a dual-chip stacking package structure includes:

[0039] substrate 6;

[0040] The first chip 1, the second chip 2, the third chip 3 and the fourth chip 4, the first chip 1 and the second chip 2 are cut into a whole; the third chip 3 and the fourth chip 4 are cut into a whole; the first chip 1 and the second chip 2 are cut into a whole; The whole cut of the chip 1 and the second chip 2 is fixed on the substrate 6 by the first adhesive film 5; Chip 2 is cut as a whole;

[0041] The package body is disposed on the substrate 6, and the first chip 1, the second chip 2, the third chip 3 and the fourth chip 4 are packaged in the package body.

[0042] The first chip 1 and the second chip 2 are electrically connected by a gold wire 7; the first chip 1 and the substrate 6 are electrically connected by a gold wire 7; the third chip 3 and the fourth chip 4 are electrically connected by a gold wire 7 is electrically connected; the fourth chip 4 and the...

Embodiment 2

[0048] A two-chip stack packaging method, comprising:

[0049] like figure 2 As shown, the scribing process: after the wafer 11 is supplied, the wafer 11 is scribed horizontally and vertically to form a dicing road 10, and a plurality of double chips 9 are formed by cutting to form a plurality of two chips connected together; reduce the vertical dicing road 10. The hourly output is increased by about 25%; the double chip 9 includes the entire cutting of the first chip 1 and the second chip 2, and the first chip 1 and the second chip 2 do not need to be cut. The whole cut of the first chip 1 and the second chip 2 and the cut whole of the third chip 3 and the fourth chip 4 are all double chips.

[0050] Core loading and wire bonding process: Grab the double chips 9, and only grab the first chip 1 and the second chip 2 once. The prior art needs to grab the first chip 1 and the second chip 2 respectively. Take, the hourly output is increased by about 50%;

[0051] Grab the whole...

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Abstract

The invention belongs to the technical field of chip packaging, and particularly discloses a double-chip stacked packaging structure and method. A first chip, a second chip, a third chip and a fourth chip, wherein the first chip and the second chip are cut into a whole; the third chip and the fourth chip are cut into a whole; the cut whole of the first chip and the second chip is fixed on the substrate; the cut whole of the third chip and the fourth chip is fixed on the cut whole of the first chip and the second chip; and the packaging body is arranged on the substrate, and the first chip, the second chip, the third chip and the fourth chip are packaged in the packaging body. According to the invention, the two chips are cut into an integral double-chip for stacking and packaging, the cut integral double-chip is grabbed in the packaging process, and the two chips in the double-chip are tiled and wired and then stacked and wired with the other double-chip, so that the yield per hour is improved, the stacking space is saved, and the product capacity is increased.

Description

technical field [0001] The invention belongs to the technical field of chip packaging, and in particular relates to a dual-chip stack packaging structure and method. Background technique [0002] The memory product market requires larger and larger capacities, thinner chips, and thinner packages. In the prior art, single-chip dicing is performed during the wafer incoming scribing process, single-chip grabbing and stacking is adopted during the chip loading process, and single-chip packaging is also used during chip packaging. The process is complex and inefficient, the package thickness is thick, and the product Small capacity. SUMMARY OF THE INVENTION [0003] In order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide a dual-chip stacking packaging structure and method, so as to solve the problem of using single-chip dicing, single-chip grabbing and stacking in the prior art, and using a single-chip for packaging efficiency...

Claims

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Application Information

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IPC IPC(8): H01L25/065H01L23/31H01L21/50H01L21/56H01L21/60
CPCH01L25/0657H01L23/3107H01L21/50H01L21/56H01L21/60H01L2021/60007H01L2224/73265H01L2224/48145H01L2224/32145H01L2924/00
Inventor 李凯
Owner 华天科技(南京)有限公司
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