Three-dimensional fan-out packaging structure and preparation method thereof

Abstract

The invention discloses a three-dimensional fan-out packaging structure and a preparation method thereof, and the method comprises the steps: digging a groove in a carrier plate, preparing a metal wiring layer at the groove and the periphery of the groove, then pasting a core particle, leading out a part of pins of the core particle to the front surface of the carrier plate through the metal wiring layer, carrying out the plastic packaging, preparing a conductive column at a plastic packaging layer, and leading out the part of pins. Then preparing a first rewiring layer and a first dielectric layer on the plastic packaging layer to complete front packaging; and thinning the back surface of the carrier plate until the metal wiring layer is formed and the other part of pins of the core particles are exposed, then preparing a second rewiring layer and a second dielectric layer, completing preparation of fan-out packaging units of double-sided fan-out, stacking the fan-out packaging units according to needs, and then connecting the fan-out packaging units by adopting solder balls to obtain the three-dimensional fan-out packaging structure. According to the fan-out packaging unit with the two fan-out surfaces, the interconnection distance can be effectively reduced, three-dimensional stacking is facilitated, the fan-out packaging unit has great advantages in electrical interconnection performance, the loss is smaller, the efficiency is higher, the packaging process difficulty is greatly reduced, and the packaging cost is reduced.

Description

A three-dimensional fan-out packaging structure and preparation method thereof technical field The invention belongs to the technical field of integrated circuit packaging, relate to a kind of fan-out packaging technology, be specifically related to a kind of three-dimensional Fan-out package structure and preparation method thereof. Background technique [0002] With the improvement of IC technology, the chip area is constantly shrinking, and the number of transistors contained in a unit area is increasing. Plus, the chip cannot accommodate enough pins per unit area, and the traditional package cannot meet the high-resolution chip package. Therefore, the high-density fan-out packaging method came into being. Wafer-level fan-out packaging is an embedded package fabricated at the wafer level. It is also a major advanced technology for the large number of input / output ports (I / O) and high integration flexibility. packaging process. It can realize vertical and horizon...

AI Technical Summary

Problems solved by technology

[0003] At present, for semiconductor stacking components, it is usually to stack multiple semiconductor chips together through bonding materials, and then use molding materials or underfill materials to package the stacked semiconductor chips to form a semiconductor stacked package structure, and in the actual application process , when different types of semiconductor chips are stacked together, due to their long interconnection distance, the performance of semiconductor chips will be unstable, which will affect their service life

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