Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a substrate on which a pattern transfer material layer is formed; forming a mask layer on the pattern transfer material layer, wherein an opening penetrating through the mask layer is formed in the mask layer; forming a side wall layer on the side wall of the opening; with the side wall layer as a mask, first ion implantation is carried out on the pattern transfer material layer at the bottom of the opening, target ions are implanted into the pattern transfer material layer, a pattern layer penetrating through the pattern transfer material layer is formed, and the target ions are used for improving the etching selection ratio between the material transfer layer and the pattern layer; and after the pattern layer is formed, removing the mask layer and the side wall layer. According to the invention, the side wall layer is formed at the opening, the target ion concentration at each position of the pattern layer can easily meet the process requirement in the direction of the thickness of the pattern layer, and meanwhile, the problem of serious transverse diffusion of the target ions at the position close to the bottom of the opening is improved, so that the side wall perpendicularity and the line width precision of the pattern layer can be improved; and therefore, the pattern transmission precision is improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background technique [0002] With the rapid growth of the semiconductor integrated circuit (integrated circuit, IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits smaller in size, higher in circuit precision, and development in the direction of higher complexity. [0003] During the development of integrated circuits, usually while the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) gradually decreases, which increases accordingly. Difficulty and complexity of integrated circuit fabrication. [0004] At present, how to improve the accuracy of graphics transfer ...

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Problems solved by technology

[0003] During the development of integrated circuits, usually while the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) gradually decreases, which increases accordingly. Difficulty and complexity of integrated circuit manufacturing

[0004] At present, how to improve the accuracy of graphics transfer has become a challenge in the case of shrinking technology nodes

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