Parameter optimization method and system of analog integrated circuit

A technology of integrated circuits and optimization methods, applied in the fields of electrical digital data processing, computational models, character and pattern recognition, etc., can solve the loss of use value, increase the difficulty of Bayesian optimization algorithm high-dimensional problems, and Bayesian optimization algorithm iteration The number of times is limited to avoid excessive computing resource overhead, improve optimization efficiency, and increase the number of iterations.

Pending Publication Date: 2022-05-13
XI AN JIAOTONG UNIV
View PDF0 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the above-mentioned existing methods optimize the more commonly used analog integrated circuits (usually the dimension is between 20 and 40), it is difficult to converge to the optimal solution under limited computing resources, resulting in loss of use value
[0006] In addition, from the perspective of computational complexity of the algorithm, since the computational complexity of Bayesian optimization based on the Gaussian process is O(n 3 ) (n is the number of iterations), under limited computing resources, the number of iterations of the Bayesian optimization algorithm is limited, which further increases the difficulty of the Bayesian optimization algorithm to deal with high-dimensional problems

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Parameter optimization method and system of analog integrated circuit
  • Parameter optimization method and system of analog integrated circuit
  • Parameter optimization method and system of analog integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0047] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is an embodiment of a part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0048] It should be noted that the terms "first" and "second" in the description and claims of the present invention and the above drawings are used to distinguish similar objects, but not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a parameter optimization method and system for an analog integrated circuit. The method comprises the following steps: acquiring a circuit structure, performance index requirements, design parameters and a value range thereof, and an iteration stop condition of the analog integrated circuit to be subjected to parameter optimization; based on the obtained design parameters and the value range thereof, sampling to obtain a training sample set; respectively inputting each sample in the training sample set into a circuit simulator for simulation to obtain a corresponding training response set; and performing iteration based on the training sample set and the training response set to realize parameter optimization of the analog integrated circuit. The invention provides a step-by-step optimization strategy based on mutual information analysis in order to alleviate the problem of curse of dimensionality and enable an algorithm to have the capability of processing a high-dimensional optimization problem. In each iteration, only part of design variables are selected for optimization, and the curse of dimensionality can be relieved.

Description

technical field [0001] The invention belongs to the technical field of analog integrated circuit design, relates to the field of Bayesian algorithm optimization, in particular to a parameter optimization method and system of an analog integrated circuit. Background technique [0002] Analog integrated circuits usually occupy a small part of the chip area of ​​the mixed-signal system-on-chip. Due to the lack of mature automatic design solutions, the parameters of analog integrated circuits need to be manually selected and adjusted. The process is time-consuming and tedious and highly dependent on the designer's intuition and According to experience, the design of analog integrated circuits has become a key bottleneck in the time to market of a SoC. With the development of machine learning, parameter optimization methods for analog integrated circuits based on machine learning have received extensive attention in recent years. [0003] The current optimization method of analo...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F30/373G06N7/00G06K9/62G06F111/04G06F111/08
CPCG06F30/373G06F2111/04G06F2111/08G06N7/01G06F18/243
Inventor 王红义陈晨惠静妮吴凯凯梁峰
Owner XI AN JIAOTONG UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products