FPGA program upgrading method and device

A technology of program upgrade and upgrade flag, which is applied in the field of optical communication, can solve the problems affecting the gain flatness of optical fiber amplifiers and the inability to continue outputting PWM waveforms, etc., and achieve the effect of making up for the lack of driving signals

Pending Publication Date: 2022-04-26
GUANGXUN SCI & TECH WUHAN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is that the FPGA program in the prior art often needs to be upgraded. During the period when the FPGA loads a new version of the program after the upgrade is completed, the FPGA port will be in a high-impedance state and cannot continue to output PWM waveforms, which will cause this. When the heating circuit stops heating for a period of time, the working environment temperature of the erbium-doped fiber will change, which in turn affects the gain flatness of the fiber amplifier.

Method used

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  • FPGA program upgrading method and device

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Embodiment 1

[0046] Embodiment 1 of the present invention provides a method for upgrading FPGA programs, such as figure 2 As shown, a data transmission link is established between the MCU and the FPGA. The 2:1MUX is controlled by the MCU. The two input ports of the 2:1MUX are respectively coupled to the PWM output port of the FPGA and the PWM output port of the MCU. The 2:1MUX The output port is coupled with the input end of the EDF temperature control drive circuit. During normal operation, the 2:1MUX is controlled by the MCU to select the PWM of the FPGA as the output signal of the output port of the 2:1MUX, and output to the EDFA temperature control circuit; if the FPGA program enters the upgrade state, such as image 3 As shown, the methods include:

[0047] In step 201, before executing the program upgrade, the FPGA sends an upgrade flag to the MCU through the data transmission link, and transmits the duty cycle information of its own PWM to the MCU.

[0048] The data transmission ...

Embodiment 2

[0076] Such as Image 6 As shown, it is a schematic diagram of the structure of the FPGA program upgrading device according to the embodiment of the present invention. The device for upgrading FPGA programs in this embodiment includes one or more processors 21 and memory 22 . in, Image 6 A processor 21 is taken as an example.

[0077] Processor 21 and memory 22 can be connected by bus or other means, Image 6 Take connection via bus as an example.

[0078] The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer-executable programs, such as the FPGA program upgrade method in Embodiment 1. The processor 21 executes the FPGA program upgrade method by running the non-volatile software programs and instructions stored in the memory 22 .

[0079] The memory 22 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk stora...

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Abstract

The invention relates to the technical field of optical communication, and provides an FPGA program upgrading method and device. Before program upgrading is executed, the FPGA sends an upgrading mark to the MCU through the data transmission link and transmits duty ratio information of PWM of the FPGA to the MCU; the MCU firstly outputs a corresponding PWM waveform to the 2: 1 MUX according to duty ratio information transmitted by the FPGA; and the MCU switches the input channel selection of the MUX from the FPGA side to the MCU side, so that the EDF temperature control drive circuit is switched from FPGA control to MCU take-over. According to the method, the influence of FPGA upgrading on the EDFA gain flatness is reduced to the minimum.

Description

【Technical field】 [0001] The invention relates to the technical field of optical communication, in particular to an FPGA program upgrading method and device. 【Background technique】 [0002] Such as figure 1 As shown, in order to obtain better gain flatness in different temperature environments in traditional fiber amplifiers, the erbium-doped fiber EDF will work under a relatively stable high temperature condition, and the circuit design will use Pulse Width Modulation (Pulse Width Modulation, abbreviated as: PWM) mode progressively controls the heating load, as follows figure 1 , the MCU is generally only responsible for communication with the FPGA, and the FPGA directly outputs the pulse width modulation PWM waveform to the EDF temperature control drive circuit behind. The defect of this design is that the FPGA program often needs to be upgraded. During the period when the FPGA loads the new version of the program after the upgrade is completed, the FPGA port will be in ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/65G05D23/20
CPCG06F8/65G05D23/20
Inventor 李春雨张翠红余春平
Owner GUANGXUN SCI & TECH WUHAN
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