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Metastable state risk avoidance method and circuit in cross-clock domain data transmission

A data transmission, cross-clock domain technology, applied in electrical digital data processing, digital computer components, generation/distribution of signals, etc. The effect of metastability risk, reducing data transmission delay, and improving system performance

Pending Publication Date: 2022-04-15
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to overcome the problem of increased risk of metastable state caused by complex voltage, clock frequency relationship between cores and PVT fluctuations in chips such as multi-core / many-core processors in the above-mentioned prior art, thereby reducing the reliability of data transmission. To provide a metastable risk avoidance method and circuit in cross-clock domain data transmission,

Method used

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  • Metastable state risk avoidance method and circuit in cross-clock domain data transmission
  • Metastable state risk avoidance method and circuit in cross-clock domain data transmission
  • Metastable state risk avoidance method and circuit in cross-clock domain data transmission

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Embodiment 1

[0040] This embodiment provides a metastable risk avoidance method in cross-clock domain data transmission, which includes constructing multiple receiver clocks with the same frequency and different phases, sampling the data of the transmitter respectively during the entire clock cycle of the receiver, and according to different The difference between the data results of the phase receiving end clock sampling the sending end, judges in real time whether there is a metastable risk when each receiving end clock samples the sending end data, and continuously switches to select the one that does not have the risk of metastable state within the preset first time The receiving end clock is used as the effective clock of the receiving end to transmit data with the sending end.

[0041] As a preferred embodiment, the sampling edges of multiple receiver clocks are distributed sequentially, and when there is a metastable risk between the current receiver clock and the data at the sender,...

Embodiment 2

[0048] This embodiment provides a metastable risk avoidance circuit in cross-clock domain data transmission, including a metastable risk prediction circuit and a clock selection circuit without a metastable risk. The metastable risk prediction circuit includes a sending end clock, an original receiving end clock, a plurality of receiver clock test modules and second delay units connected in sequence, the receiver clock test modules include a detection unit and a first delay unit, and the first delay units in each receiver clock test module are connected in sequence, A second delay unit is also connected between two adjacent first delay units, and the two ends of the first delay unit are respectively connected to the detection unit;

[0049] The first delay unit at one end of all receiving-end clock test modules is connected to the original receiving-end clock, and the other end is connected to the sending-end clock through a frequency divider. unit;

[0050] The frequency div...

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Abstract

The invention relates to a metastable-state risk avoidance method and circuit in cross-clock-domain data transmission, and the method comprises the steps: constructing a plurality of receiving end clocks with the same frequency and different phases, sampling transmitting end data in the whole receiving end clock period, and determining the metastable-state risk in the cross-clock-domain data transmission according to the difference of the transmitting end data sampling results of the receiving end clocks with different phases. And judging whether each receiving end clock has a metastable state risk when sampling the data of the sending end in real time, and continuously switching and selecting the receiving end clocks which do not have risks in a future period of time to carry out data communication with the sending end. Compared with the prior art, the method has the advantages that the potential metastable risk can be predicted in advance, and the phase of the effective clock of the receiving end is adaptively adjusted to avoid the imminent metastable risk, so that the reliability of cross-clock domain data transmission is ensured; moreover, the method can be applied to cross-clock domain data transmission of different frequency relationships through simple modeling simulation, does not need to carry out a data test or experiment in advance, and is convenient to use.

Description

technical field [0001] The invention relates to the technical field of processor data processing, in particular to a metastable risk avoidance method and circuit in cross-clock domain data transmission. Background technique [0002] On a multi-core / many-core chip, there may be different voltages and clock frequencies between cores and between different modules in a single core, resulting in the phase relationship between the data at the sending end and the sampling clock at the receiving end changing over time. This will cause that when the timing unit at the receiving end samples the data at the sending end, the data change edge at the sending end may be very close to the sampling edge of the clock at the receiving end. At this time, because the phase relationship between the data at the sending end and the clock at the receiving end violates the setup time and hold time requirements of the sequential unit, the sequential unit cannot sample data correctly, and its output wi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/163G06F1/12
Inventor 何卫锋林初雄邵琳
Owner SHANGHAI JIAO TONG UNIV
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