Processor-oriented data transmission instruction implementation method and system

Abstract

The invention provides a processor-oriented data transmission instruction implementation method and system, and the method comprises the following steps: S1, carrying out the decoding of an RISC special processor to obtain a memory reading instruction, and moving the data of a specific length byte from a memory to a plurality of specified registers according to a memory address and a register head address given in the instruction; and S2, decoding by the RISC special processor to obtain a write memory instruction, and moving data of bytes with specific length from the register to a specified memory address according to the memory address given in the instruction and the initial address of the register. According to the method and the device, multi-data rapid moving operation is realized; the multi-data transmission instruction has the advantages of flexible addressing mode and the like, so that the operation efficiency of the multi-data transmission instruction is improved, the multi-data migration operation in the application of the special processor is facilitated, and particularly, the operation efficiency of the special processor is greatly improved due to the fact that a large amount of data generally needs to be rapidly and sequentially migrated in the field of network processors.

Description

technical field [0001] The present invention relates to the technical field of computers, in particular to a method and system for implementing a processor-oriented data transmission instruction, and in particular to a method for implementing a special-purpose processor-oriented multi-data transmission instruction. Background technique [0002] In the early days of computer development, the cost of memory was high, so it was hoped to achieve as many computer operations as possible with as few instructions as possible, thereby reducing the storage resources consumed by calculator programs, which led to the formation of the CISC design style. That is, relying on increasing instruction complexity and functions to improve computer performance. The processor based on the CISC architecture has a strong ability to process high-level languages, so the amount of code is small, but in order to cope with different computer operations, the complexity of hardware design is usually high. ...

AI Technical Summary

Problems solved by technology

[0012] The Load / Store instruction in the proposed RISC instruction set either has a small data throughput and cannot take advantage of the performance of a high-speed bus, or has poor flexibility and cannot meet the needs of a special-purpose processor

With the development of technology, higher and higher requirements are put forward for data communication and processing speed, especially in the field of specific embedded special-purpose processors, such as network processors, where a large number of uncertainties usually occur in a short period of time. Data exchange, so traditional Load / Store instructions will not be able to meet the resulting real-time requirements

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