Wafer level chip size packaging structure and manufacturing method thereof

Abstract

The invention provides a wafer level chip size packaging structure and a manufacturing method thereof. The wafer level chip size packaging structure comprises a first chip, a redistribution circuit layer, a plurality of ball bottom metal layers, a plurality of conductive columns, a second chip, packaging colloid and a plurality of connecting parts. The redistribution circuit layer is disposed on the first chip and electrically connected to pads thereof. The ball bottom metal layers are on the redistribution circuit layer. The conductive columns are located on a part of the ball bottom metal layers. The second chip is located on the other part of the ball bottom metal layers. The second chip has an active surface facing the plurality of ball bottom metal layers. The conductive columns surround the second chip. The packaging colloid at least packages the second chip and part of the side walls of the conductive columns. The top surface of the packaging colloid is lower than the top surfaces of the conductive columns. The connecting parts are located on the conductive columns and are electrically connected with the redistribution circuit layer through the conductive columns and the ball bottom metal layers. The connecting parts extend to the top surface of the packaging colloid.

Description

technical field [0001] The invention relates to a packaging structure and a manufacturing method thereof, in particular to a wafer-level chip size packaging structure and a manufacturing method thereof. Background technique [0002] Wafer level packaging technology (Wafer Level Packaging) is a packaging technology that performs chip size on the entire wafer, that is, most of the packaging work is completed at the wafer stage. Therefore, wafer level chip size packaging can reduce packaging Body size, and also quite advantageous in terms of process and material cost. [0003] Generally speaking, there are many factors affecting the reliability of WLCSP. For example, if the components on the wafer have poor bonding strength or are damaged during the process, it will have a bad impact on the WLCSP, thereby reducing the reliability of the WLCSP. Therefore, how to reduce the occurrence of adverse effects on the WLCSP, thereby improving the reliability of the WLCSP, has become a ...

AI Technical Summary

Problems solved by technology

[0004] The present invention is directed to a wafer-level chip size packaging structure and a manufacturing method thereof, which can reduce the occurrence of adverse effects on the wafer-level chip size packaging structure, thereby improving the reliability of the wafer-level chip size packaging structure

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