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Formation method of semiconductor structure

A technology of semiconductor and isolation structure, which is applied in the field of semiconductor structure formation to achieve the effect of simplifying process flow, improving production efficiency and improving performance

Pending Publication Date: 2021-10-12
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, as the size of the device shrinks, there are many problems in the method of making the polysilicon dummy gate, and a new method is needed to improve the performance of the formed semiconductor structure.

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Embodiment Construction

[0028] As mentioned in the background, the existing method for fabricating polysilicon dummy gates needs to be improved. Now analyze and illustrate in conjunction with specific embodiment.

[0029] figure 1 and figure 2 They are respectively a top view and a cross-sectional schematic diagram of a semiconductor structure in an embodiment.

[0030] Please refer to figure 1 and figure 2 , figure 1 for figure 2 top view of figure 2 for figure 1 A schematic cross-sectional structure along the section line AA', wherein the section line AA' extends along the direction of the dummy gate structure, including: a substrate 100 including a first region I, a second region II and an isolation region III, the isolation region III is located between the first region I and the second region II, the first region I and the second region II have a fin structure 101; the first dielectric layer 102 on the substrate 100, The first dielectric layer 102 is located on the sidewall of the f...

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Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; forming a plurality of fin structures on the substrate, wherein each fin structure comprises an effective region and a to-be-isolated region which are distributed in the direction parallel to the surface of the substrate, the top surface of each effective region is provided with a first barrier layer, and the top surface of each to-be-isolated region is provided with a second barrier layer; removing the first barrier layer; after the first barrier layer is removed, forming an initial dummy gate structure on the substrate and the fin structures, wherein the initial dummy gate structure crosses the plurality of fin structures, and the top of the initial dummy gate structure exposes the second barrier layer on the top surface of the to-be-isolated region; removing the second barrier layer on the top surface of the to-be-isolated region; after the second barrier layer is removed, removing part or all of the to-be-isolated regions, and forming isolation openings in the initial dummy gate structures, wherein the bottom planes of the isolation openings are lower than or flush with the bottom planes of the initial dummy gate structures; and forming a first isolation structure in the isolation opening. The method improves the performance of the semiconductor structure.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] In recent years, Fin Field Effect Transistor (FinFET) has been widely used because it can effectively control the short-channel effect caused by the shrinking of the critical dimension of the device. In the manufacture of fin field effect transistors, the manufacture of polysilicon dummy gate (Poly-Si Dummy Gate) generally uses two masks, the first mask is used to form polysilicon lines after polysilicon deposition, and the second mask Used to cut polysilicon wire. Compared with using a single mask to make a polysilicon dummy gate, using a double mask to make a polysilicon dummy gate can obtain a rectangular dummy gate profile (that is, the end of the cut polysilicon line is close to a right-angled rectangle instead of an arc), which is convenient Greater control over gate patterns leads to ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78H01L29/06
CPCH01L29/66795H01L29/785H01L29/66545H01L29/0649
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP
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