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Large-size chip, manufacturing method thereof and large-size chip wafer

A production method and large-size technology, applied in the field of large-size chips and their production, and large-size chip wafers, can solve problems such as functional integration that needs to be improved

Active Publication Date: 2021-09-14
WUHAN XINXIN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003]In actual application, the functional integration between the small splicing chips on the large size chip needs to be improved

Method used

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  • Large-size chip, manufacturing method thereof and large-size chip wafer
  • Large-size chip, manufacturing method thereof and large-size chip wafer
  • Large-size chip, manufacturing method thereof and large-size chip wafer

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Embodiment Construction

[0053] Based on the above research, an embodiment of the present invention provides a method for manufacturing a large-size chip. The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0054] The embodiment of the present invention provides a method for manufacturing a large-size chip, such as figure 1 shown, including:

[0055] A wafer is provided, the wafer includes several large-size chips, the size of the large-size chips is larger than the maximum exposure field of view of the photolithography machine; the large-size chip includes at least two spliced ​​chips, adjacent to...

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Abstract

The invention provides a large-size chip, a manufacturing method thereof and a large-size chip wafer. The manufacturing method comprises the steps that a wafer is provided, the wafer comprises a plurality of large-size chips, and the size of each large-size chip is larger than the maximum exposure view field of a photoetching machine; the large-size chip comprises at least two splicing chips; each splicing chip comprises a substrate and a first metal layer, and the first metal layer at least comprises a to-be-interconnected metal layer used for interconnection between different splicing chips; and a second metal layer is formed, the second metal layer at least comprises an inter-chip interconnection metal layer, and the inter-chip interconnection metal layer spans the virtual scribing area between the adjacent splicing chips and is electrically connected with the respective metal layers to be interconnected of the adjacent splicing chips. According to the invention, interconnection between different splicing chips is realized on a large-size chip, and electric signal interconnection optimization of a large-size chip level is realized through interconnection function expansion of small splicing chips, so that integration of more functions is realized, and flexibility and compatibility are realized.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a large-size chip, a manufacturing method thereof, and a large-size chip wafer. Background technique [0002] In traditional lithography, the size of a single chip is smaller than or equal to the maximum exposure field of view of the lithography machine, and a single exposure completes the lithography of a single chip. With the development of semiconductor technology, chips play a wider role in various fields. In some fields, large-scale chips (such as high-speed computing chips) are required, and the size of these large-scale chips has exceeded the maximum size of the lithography machine. Exposure field of view (for example, 26mm×33mm), so in the manufacturing process, stitching technology needs to be used. As the name implies, in the chip manufacturing process, one splicing chip is formed by one exposure, multiple splicing chips are formed ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/56H01L23/498H01L23/528
CPCH01L21/561H01L23/49811H01L23/528H01L23/544H01L2223/54426H01L25/0652G03F7/70475G01N2223/6116G03F7/70633H01L21/682H01L2223/54466
Inventor 胡胜周俊孙鹏占琼施森华杨虎
Owner WUHAN XINXIN SEMICON MFG CO LTD
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