A Fault-Tolerant Mapping Method for Optimizing Power Consumption in Nanoscale CMOS Circuits

A mapping method and circuit technology, applied in the field of integrated circuits, can solve problems such as increased power consumption of nano-CMOS circuits, and achieve the effects of improving solution speed, reducing the influence of circuit fault-tolerant complexity, and optimizing power consumption

Active Publication Date: 2022-05-17
NINGBO UNIV
View PDF10 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] The technical problem to be solved by the present invention is to provide a fault-tolerant mapping method for nano-CMOS circuits that can optimize power consumption for the problem that the defects of nano-CMOS circuits lead to increased circuit power consumption

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A Fault-Tolerant Mapping Method for Optimizing Power Consumption in Nanoscale CMOS Circuits
  • A Fault-Tolerant Mapping Method for Optimizing Power Consumption in Nanoscale CMOS Circuits
  • A Fault-Tolerant Mapping Method for Optimizing Power Consumption in Nanoscale CMOS Circuits

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0075] Embodiment 1: using the fault-tolerant mapping method of the present invention, the Figure 7 The logic circuit shown with 8 nodes maps to Figure 8 Defect nanoscale CMOS circuit of 4 x 4 size is shown. exist Figure 7 In the logic circuit of , there are 3 original inputs {i 1 ,i 2 ,i 3}, 3 logical nodes {g 1 , g 2 , g 3}, 2 raw outputs {o 1 ,o 2}, each node is coded according to the integer {i 1 ,i 2 ,i 3 , g 1 , g 2 , g 3 ,o 1 ,o 2}→{0,1,2,3,4,5,6,7}. exist Figure 8 In the nano-CMOS circuit of , the black dots on the nano-wires represent nano-diodes with normally connected defects. The normal nano-devices are not shown, and the units A, B, C, D, and E are normally-connected units. According to their positions in the circuit, they are From bottom to top and from left to right, it is encoded as {D,C,B,A,E}→{0,1,2,3,4}, and stored in the set P. Assuming that the radius of the connected domain is large enough, each unit is in the connected domain of e...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a nano-CMOS circuit fault-tolerant mapping method that can optimize power consumption. Aiming at the problem that the defects of the nano-CMOS circuit increase the power consumption of the circuit, the method of the invention first uses the packaging technology to pack the high-level constant-connected units and their The constant output is packaged into a unit package, and the associated nodes are selected to generate a certain number of node packages; then the circuit fault-tolerant mapping is completed by using the genetic algorithm, and the one-to-one matching mapping between the unit package and the node package is guaranteed through specific genetic coding methods and crossover and mutation operations , to reduce the complexity of fault tolerance, and absorb the power consumption optimization constraints into the fitness function to optimize the power consumption of the mapping solution. The method of the invention can effectively reduce the circuit fault-tolerant complexity, and realize power consumption optimization of the mapping circuit on the basis of quickly eliminating the influence of defects on the logic function of the mapping circuit.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a nanometer CMOS circuit fault-tolerant mapping method capable of optimizing power consumption. Background technique [0002] As devices reach their physical limits, traditional integrated circuit technology faces many problems such as increased quantum effects and skyrocketing manufacturing costs. Researchers believe that using emerging nanoelectronic devices and corresponding nanocircuits, higher integration density and operating frequency can be obtained, thereby continuing the development of integrated circuits. Among them, the CMOS / nanowire / molecular hybrid (CMOS / nanowire / molecular hybrid, CMOL) circuit proposed by the Likharev research team of Stony Brook University in the United States is considered to be It is one of the most promising CMOS alternative technologies, and has been successfully applied in high-speed mass memory, field programmable gate array and artificia...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/327G06N3/12
CPCG06F30/327G06N3/126Y02D10/00
Inventor 夏银水谢尚銮查晓婧
Owner NINGBO UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap