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Register set circuit device supporting out-of-order multi-read-write

A technology of register groups and registers, applied in the direction of instruments, electrical digital data processing, special data processing applications, etc.

Pending Publication Date: 2021-07-09
苏州芯启微电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The invention provides a multi-port register bank circuit device supporting out-of-order, which mainly solves the problem of writing to the same register at the same time by multiple ports in a superscalar processor capable of out-of-order execution, and the problem of "write after write" of any register

Method used

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  • Register set circuit device supporting out-of-order multi-read-write
  • Register set circuit device supporting out-of-order multi-read-write
  • Register set circuit device supporting out-of-order multi-read-write

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Embodiment Construction

[0030] The present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0031] figure 1 It is a hardware structural diagram of a multi-port register bank file that supports out-of-order in the present invention, and the hardware device includes:

[0032] Multiple write ports, each for receiving write data;

[0033] The multi-port out-of-sequence write selection controller is used to process the priority level when multiple write ports are jointly accessed according to the identification number of each port, and generate a write enable generation signal for each port;

[0034] The multi-port write selection array is controlled by the write selection signal, and outputs the write data in the form of an AND or gate design;

[0035] Other necessary components that constitute the register file device include: the storage body of the register file composed of multiple register windows, where each register window includes m...

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Abstract

The invention relates to a register set circuit device supporting out-of-order multiple read-write. The circuit device comprises a multi-port out-of-order write selection controller, a multi-port write selection array, a write instruction queue and a register set file. The circuit is used for a sequential or out-of-order multi-emission multi-execution processor, and the out-of-order multi-read and multi-write problem of a register block circuit is solved. The register set file comprises a specific write selection controller, and a specific assembly line control mechanism based on identifiers is achieved.

Description

technical field [0001] The invention belongs to the field of computer hardware, superscalar processor design, and digital integrated circuit design, and in particular relates to a processor core micro-architecture and a register group file device. Background technique [0002] The superscalar processor has a hardware device for issuing multiple instructions and multiple execution units execute the issued instructions in parallel. Multiple execution units are adapted to different instruction functions, and the execution time of each execution process is different, resulting in codes that are issued at the same time. The order in which the execution ends is different, resulting in out-of-order writing after execution. [0003] There are also superscalar processor designs that introduce out-of-order launches during the instruction launch phase, combined with different end times for multiple executions, and more generally cause out-of-order writebacks. [0004] Patent CN1501292...

Claims

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Application Information

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IPC IPC(8): G06F30/373
CPCG06F30/373
Inventor 杨旭光
Owner 苏州芯启微电子科技有限公司
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