High-yield wafer-level filter chip packaging structure and method

A chip packaging structure and filter technology, which is applied in the manufacturing of electric solid state devices, semiconductor devices, and semiconductor/solid state devices, etc., can solve the problems of large product size, inconsistent product matching, and high cost.

Pending Publication Date: 2021-05-14
阿尔伯达(上海)科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Traditional filter packages (including metal shell packages, plastic packages, or surface-mount packages, etc.), have large product sizes, relatively expensive costs, and inconsistent matching of various products, which have gradually failed to meet the needs of terminals.

Method used

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  • High-yield wafer-level filter chip packaging structure and method
  • High-yield wafer-level filter chip packaging structure and method
  • High-yield wafer-level filter chip packaging structure and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0029] Such as Figure 1 to Figure 4 As shown, a high-yield wafer level 1 filter chip packaging structure, filter chip and substrate 6, the filter chip is connected to the substrate 6, the filter chip includes a wafer 1, a plurality of welding pads 4. The cofferdam 2 and the cover 3, the welding pad 4 is arranged beside the wafer 1 with a plurality of welding pads 4, the wafer 1 is surrounded by a cofferdam 2, and above the cofferdam 2 is a A cover 3, the cover 3 is closely attached to the top of the cofferdam 2, a sealed cavity 9 is formed between the wafer 1, the cofferdam 2 and the cover 3, and a welding layer 10 is electroplated or chemically plated on the welding pad 4, and the Solder balls or gold balls 5 are arranged above the solder layer 10;

[0030] The substrate 6 is provided with a plurality of metal pads 7 and solder resist oil, the metal pads 7 are soldered to the solder balls or gold balls 5, and grooves 8 are arranged between the plurality of metal pads 7 , t...

Embodiment 2

[0038] Such as Figure 5 Shown, a kind of high yield filter chip packaging method, described method comprises:

[0039] Step 1: Fabricate the cofferdam 2 on the wafer 1 by using glue exposure and development technology, the cofferdam 2 surrounds the wafer 1; the cofferdam 2 is arranged between the wafer 1 and the solder Between the pads 4, the glue coating speed formed by the cofferdam 2 is between 500-1000rpm, the exposure energy of the cofferdam 2 is 150-250mj, the development time of the cofferdam 2 is 200-280s, and the cofferdam 2 is formed During the process, the main rotation speed of glue coating is preferably 800RPM, the exposure energy is 200mj, and the developing time is 240s. The width of the cofferdam 2 is greater than 10um, which is convenient for the operation of step 2.

[0040] Step 2: On the cofferdam 2, the cover 3 is made by film exposure and development, and a sealed cavity 9 is formed between the chip, the cofferdam 2 and the cover 3; the cover 3 is prefe...

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Abstract

The invention discloses a high-yield wafer-level filter chip packaging structure and method. The high-yield wafer-level filter chip packaging structure comprises a filter chip and a substrate, wherein the filter chip is connected with the substrate, the filter chip comprises a wafer, a plurality of welding pads, a cofferdam and a cover, the welding pads are arranged beside the wafer, the cofferdam is arranged on the periphery of the wafer, the cover is arranged above the cofferdam, the cover clings to the upper part of the cofferdam, a sealing cavity is formed among the wafer, the cofferdam and the cover, a welding layer is electroplated or chemically plated on the welding pads, and solder balls or gold balls are arranged on the welding layer; and the substrate is provided with a plurality of metal bonding pads and solder resist oil, the metal bonding pads are welded with the solder balls or the gold balls, a groove is formed among the plurality of metal bonding pads, and the cover is arranged in the groove. According to the high-yield wafer-level filter chip packaging structure and the method, a plurality of cavity environments are provided for the wafer, the strength of the cover is improved, the qualified efficiency of a product is improved, and the packaging cost can be greatly reduced; and the solder balls or gold balls are planted on the welding pads on the surface of the chip, so that the qualified efficiency in the inversion process can be greatly improved.

Description

technical field [0001] The invention relates to a semiconductor package structure, in particular to a high-yield wafer-level filter chip package structure and method. Background technique [0002] As the modes and frequency bands supported by the wireless mobile communication system continue to increase, the RF front-end architecture of the current wireless communication mobile terminal also becomes more and more complex. The semiconductor modularization in the front stage of approval is the general trend. Due to the limitation of equipment and terminal space, the newly added RF front-ends in the 5G era mainly appear in the form of modules, and more and more devices are integrated in the modules. Traditional filter packages (including metal shell packages, plastic packages, or surface-mount packages, etc.), have large product sizes, relatively expensive costs, and inconsistent matching of various products, which have gradually failed to meet the needs of the terminal. Con...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/488H01L21/56H01L21/78
CPCH01L23/3121H01L23/488H01L21/56H01L21/78
Inventor 于涛
Owner 阿尔伯达(上海)科技有限公司
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