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Lead wire frame

A lead frame and frame technology, which is applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of inconvenient connection of a single lead frame and low production efficiency, and achieve the effects of high positioning accuracy, improved quality, and accurate contact position

Pending Publication Date: 2021-05-07
四川富美达微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since multi-chip semiconductor devices have many pins, and the chips are solidified on the top and bottom of the pins, it is not convenient to use a single lead frame combined with a jumper for connection. This method requires multiple flips of the lead frame. Assembly and multiple welding curing, resulting in low production efficiency

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0047] Such as Figures 1 to 19 As shown, a lead frame is used to package a semiconductor device. The semiconductor device includes a package body, a first pin 1, a second pin 2, a third pin 3, a fourth pin 4 and a plurality of chips. Embodiment The present invention is described in detail by taking a semiconductor device with 4 chips as an example. The first pin 1 , the second pin 2 , the third pin 3 and the fourth pin 4 are respectively arranged on different lead frames.

[0048]The lead frame includes a middle frame 10 , a bottom frame 20 and a top frame 30 . The first pin 1 and the second pin 2 are set on the middle frame 10, the third pin 3 is set on the bottom frame 20, the fourth pin 4 is set on the top frame 30, the first pin 1 and the second pin 2 , the third pin 3 and the fourth pin 4 are formed by stamping with their respective frames.

[0049] Such as Figure 4 Both the shown first pin 1 and the second pin 2 have a welding plate 101 for connecting the chip, suc...

Embodiment 2

[0057] The pin layout of the semiconductor device can be adopted as Figure 16 , Figure 17 The structure shown, such as figure 1 As shown, the first pin 1 and the second pin 2 are arranged on the same side of the rectangular cavity 5 of the middle frame 10, as Figure 5 and Figure 9 The third pin 3 and the fourth pin 4 shown are respectively arranged in the rectangular cavity 5 of each frame, and are located on the opposite side of the first pin 1 and the second pin 2 .

Embodiment 3

[0059] The pin arrangement of the semiconductor device can also be adopted such as Figure 18 In the structure shown, the first pin 1 and the second pin 2 are respectively arranged on both sides of the rectangular cavity 5 of the middle frame 10, and the third pin 3 and the fourth pin 4 are arranged in the rectangular cavity 5 of each frame. , and are located on opposite sides.

[0060] Assembly method: place the bottom frame 20 on the jig, inject solder into the support plate 301, place the chip on the solder of the support plate 301, stack the middle frame 10 so that the first bump 102 is accurately pressed on the chip, Solder is injected into the upper surface of the soldering plate 101, the chip is placed above the solder of the soldering plate 101, and the top frame 30 is stacked. After assembly, it is as follows: Figure 19 status shown. Then it can enter the curing process for curing. After the curing is completed, follow-up work such as encapsulation and punching is...

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Abstract

A lead wire frame is used for packaging a semiconductor device and comprises a middle frame, a bottom-layer frame and a top-layer frame, wherein a first pin and a second pin are arranged on the middle frame, a third pin is arranged on the bottom-layer frame, and a fourth pin is arranged on the top-layer frame. The first pin and the second pin are provided with welding plates, the welding plates are provided with downward first protruding points, the third pin is provided with a supporting plate corresponding to the welding plates, and a chip is arranged between the upper surface of the supporting plate and the bottom faces of the first protruding points. The fourth pin is provided with a pressing plate corresponding to the welding plate, the bottom part of the pressing plate is provided with downward second salient points corresponding to the first salient points, and a chip is arranged between the upper surface of the welding plate and the bottom surfaces of the second salient points. The bottom-layer frame, the middle frame and the top-layer frame are overlapped and assembled from bottom to top, the top-layer frame, the middle frame and the bottom-layer frame respectively have a plurality of rectangular cavities which correspond to each other up and down, and a plurality of semiconductor device packaging regions are formed in the rectangular cavities along the length direction in an array manner. The lead wire frame facilitates the packaging of a multi-chip semiconductor device, and has relatively high production efficiency.

Description

technical field [0001] The present application relates to semiconductor packaging technology, in particular to a lead frame. Background technique [0002] Semiconductor devices usually solidify the chip by a lead frame, then use insulating material to plastic seal, and form a single semiconductor device after punching. Semiconductor devices are divided into single-chip and multi-chip. Most of the existing single-chips use jumpers and pins on the single-chip lead frame to fix the chip and realize the connection structure to form a semiconductor device. However, since multi-chip semiconductor devices have many pins, and the chips are solidified on the top and bottom of the pins, it is not convenient to use a single lead frame combined with a jumper for connection. This method requires multiple flips of the lead frame. Assembling and multiple welding and solidification lead to low production efficiency. Contents of the invention [0003] In order to solve the disadvantages ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L23/31
CPCH01L23/49503H01L23/49527H01L23/49541H01L23/3121
Inventor 曾尚文陈久元杨利明
Owner 四川富美达微电子有限公司
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